Intel S2600GZ S2600GZ/GL - Page 120

Timing Requirements

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Intel® Server Board S2600GZ/GL TPS Power Supply Specification Guidelines 11.2.15 Timing Requirements These are the timing requirements for the power supply operation. The output voltages must rise from 10% to within regulation limits (Tvout_rise) within 5 to 70ms. For 12VSB, it is allowed to rise from 1.0 to 25ms. All outputs must rise monotonically. The following table shows the timing requirements for the power supply being turned on and off from the AC input, with PSON held low and the PSON signal, with the AC input applied. Table 53. Timing Requirements Item Tvout_rise Tsb_on_delay T ac_on_delay Tvout_holdup Tpwok_holdup Tpson_on_del ay T pson_pwok Tpwok_on T pwok_off Tpwok_low Tsb_vout T12VSB_holdu p Description Output voltage rise time Delay from AC being applied to 12VSBbeing within regulation. Delay from AC being applied to all output voltages being within regulation. Time 12Vl output voltage stay within regulation after loss of AC. Delay from loss of AC to de-assertion of PWOK Delay from PSON# active to output voltages within regulation limits. Delay from PSON# deactivate to PWOK being deasserted. Delay from output voltages within regulation limits to PWOK asserted at turn on. Delay from PWOK de-asserted to output voltages dropping out of regulation limits. Duration of PWOK being in the de-asserted state during an off/on cycle using AC or the PSON signal. Delay from 12VSBbeing in regulation to O/Ps being in regulation at AC turn on. Time the 12VSBoutput voltage stays within regulation after loss of AC. MIN 5.0 * 13 12 5 100 1 100 50 70 * The 12VSBoutput voltage rise time shall be from 1.0ms to 25ms MAX 70 * 1500 3000 400 5 500 1000 UNITS ms ms ms ms ms ms ms ms ms ms ms ms Revision 1.1 107 Intel order number G24881-004

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IntelĀ® Server Board S2600GZ/GL TPS
Power Supply Specification Guidelines
Revision 1.1
Intel order number G24881-004
107
11.2.15
Timing Requirements
These are the timing requirements for the power supply operation.
The output voltages must
rise from 10% to within regulation limits (T
vout_rise
) within 5 to 70ms. For 12VSB, it is allowed to
rise from 1.0 to 25ms.
All outputs must rise monotonically
. The following table shows the
timing requirements for the power supply being turned on and off from the AC input, with PSON
held low and the PSON signal, with the AC input applied.
Table 53. Timing Requirements
Item
Description
MIN
MAX
UNITS
T
vout_rise
Output voltage rise time
5.0 *
70 *
ms
Tsb_on_delay
Delay from AC being applied to 12VSBbeing
within regulation.
1500
ms
T ac_on_delay
Delay from AC being applied to all output voltages
being within regulation.
3000
ms
Tvout_holdup
Time 12Vl output voltage stay within regulation
after loss of AC.
13
ms
Tpwok_holdup
Delay from loss of AC to de-assertion of PWOK
12
ms
Tpson_on_del
ay
Delay from PSON# active to output voltages
within regulation limits.
5
400
ms
T pson_pwok
Delay from PSON# deactivate to PWOK being de-
asserted.
5
ms
Tpwok_on
Delay from output voltages within regulation limits
to PWOK asserted at turn on.
100
500
ms
T pwok_off
Delay from PWOK de-asserted to output voltages
dropping out of regulation limits.
1
ms
Tpwok_low
Duration of PWOK being in the de-asserted state
during an off/on cycle using AC or the PSON
signal.
100
ms
Tsb_vout
Delay from 12VSBbeing in regulation to O/Ps
being in regulation at AC turn on.
50
1000
ms
T12VSB_holdu
p
Time the 12VSBoutput voltage stays within
regulation after loss of AC.
70
ms
* The 12VSBoutput voltage rise time shall be from 1.0ms to 25ms