Intel S2600GZ S2600GZ/GL - Page 237

CATERR, P0 MSID Mismatch, CPU Missing, P1 MSID Mismatch, P1 VRD Hot, P2 VRD Hot

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Appendix B: Integrated BMC Sensor Tables Intel® Server Board S2600GZ/GL TPS Full Sensor Name (Sensor name in SDR) Sensor # Processor 1 ERR2 Timeout 7Ch (P1 ERR2) Processor 2 ERR2 Timeout 7Dh (P2 ERR2) Catastrophic Error 80h (CATERR) Processor0 MSID Mismatch 81h (P0 MSID Mismatch) Processor Population Fault 82h (CPU Missing) Processor1 MSID Mismatch 87h (P1 MSID Mismatch) Processor 1 VRD Temperature 90h (P1 VRD Hot) Processor 2 VRD Temperature 91h (P2 VRD Hot) Processor 1 Memory VRD Hot 0-1 94h (P1 Mem01 VRD Hot) Processor 1 Memory VRD Hot 2-3 95h (P1 Mem23 VRD Hot) Platform Applicability All All All All All All All All All All Sensor Type Event/Readi Event Offset Triggers ng Type Processor 07h Processor 07h Processor 07h Processor 07h Processor 07h Processor 07h Temperature 01h Temperature 01h Temperature 01h Temperature 01h Digital Discrete 03h Digital Discrete 03h Digital Discrete 03h Digital Discrete 03h Digital Discrete 03h Digital Discrete 03h Digital Discrete 05h Digital Discrete 05h Digital Discrete 05h Digital Discrete 05h 01 - State Asserted 01 - State Asserted 01 - State Asserted 01 - State Asserted 01 - State Asserted 01 - State Asserted 01 - Limit exceeded 01 - Limit exceeded 01 - Limit exceeded 01 - Limit exceeded Contrib. To System Status fatal fatal fatal fatal Fatal fatal Non-fatal Non-fatal Non-fatal Non-fatal Assert/ De- assert As and De Readable Value/Of fsets - As and - De As and - De As and - De As and - De As and - De As and - De As and - De As and - De As and - De Event Data Trig Offset Trig Offset Trig Offset Trig Offset Trig Offset Trig Offset Trig Offset Trig Offset Trig Offset Trig Offset Rearm A A M M M M M M A A Standby 224 Revision 1.1 Intel order number G24881-004

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Appendix B: Integrated BMC Sensor Tables
Intel® Server Board S2600GZ/GL TPS
Revision 1.1
Intel order number G24881-004
224
Full Sensor Name
(Sensor name in SDR)
Sensor
#
Platform
Applicability
Sensor Type
Event/Readi
ng Type
Event Offset Triggers
Contrib. To
System Status
Assert/
De-
assert
Readable
Value/Of
fsets
Event
Data
Rearm
Stand-
by
Processor 1 ERR2 Timeout
(P1 ERR2)
7Ch
All
Processor
07h
Digital
Discrete
03h
01
–
State Asserted
fatal
As
and
De
–
Trig Offset
A
–
Processor 2 ERR2 Timeout
(P2 ERR2)
7Dh
All
Processor
07h
Digital
Discrete
03h
01
–
State Asserted
fatal
As
and
De
–
Trig Offset
A
–
Catastrophic Error
(CATERR)
80h
All
Processor
07h
Digital
Discrete
03h
01
–
State Asserted
fatal
As
and
De
–
Trig Offset
M
–
Processor0 MSID Mismatch
(P0 MSID Mismatch)
81h
All
Processor
07h
Digital
Discrete
03h
01
–
State Asserted
fatal
As
and
De
–
Trig Offset
M
–
Processor Population Fault
(CPU Missing)
82h
All
Processor
07h
Digital
Discrete
03h
01
–
State Asserted
Fatal
As
and
De
–
Trig Offset
M
–
Processor1 MSID Mismatch
(P1 MSID Mismatch)
87h
All
Processor
07h
Digital
Discrete
03h
01
–
State Asserted
fatal
As
and
De
–
Trig Offset
M
–
Processor 1 VRD
Temperature
(
P1 VRD Hot
)
90h
All
Temperature
01h
Digital
Discrete
05h
01 - Limit exceeded
Non-fatal
As
and
De
–
Trig Offset
M
–
Processor 2 VRD
Temperature
(
P2 VRD Hot
)
91h
All
Temperature
01h
Digital
Discrete
05h
01 - Limit exceeded
Non-fatal
As
and
De
–
Trig Offset
M
–
Processor 1 Memory VRD
Hot 0-1
(P1 Mem01 VRD Hot)
94h
All
Temperature
01h
Digital
Discrete
05h
01 - Limit exceeded
Non-fatal
As
and
De
–
Trig Offset
A
–
Processor 1 Memory VRD
Hot 2-3
(P1 Mem23 VRD Hot)
95h
All
Temperature
01h
Digital
Discrete
05h
01 - Limit exceeded
Non-fatal
As
and
De
–
Trig Offset
A
–