Intel S2600GZ S2600GZ/GL - Page 32

Intel® Server Board S2600GZ/GL TPS Product Architecture Overview Table 5. LRDIMM Support Guidelines Ranks Per DIMM & Data Width1 QRx4 (DDP)6 QRx8 (P)6 Memory Capacity Per DIMM2 16GB 32GB 8GB 16GB Speed (MT/s) and Voltage Validated by Slot per Channel (SPC) and DIMM Per Channel (DPC)3,4,5 2 Slots per Channel 3 Slots per Channel Intel® Sever Board S2600GL Intel® Sever Board S2600GZ 1DPC and 2DPC 1DPC and 2DPC 3DPC 1.35V 1.5V 1.35V 1.5V 1.35V 1066 1066, 1333 1066 1066, 1333 1066 1066 1066, 1333 1066 1066 1066 1.5V 1066 1066 3.2.4.2 Memory Slot Identification and Population Rules Note: Although mixed DIMM configurations may be functional, Intel only performs platform validation on systems that are configured with identical DIMMs installed.  Each installed processor provides four channels of memory. On the Intel® Server Board S2600GZ each memory channel supports three memory slots, for a total possible 24 DIMMs installed. On the Intel® Server Board S2600GL each memory channel supports 2 memory slots, for a total possible 16 DIMMs installed.  System memory is organized into physical slots on DDR3 memory channels that belong to processor sockets.  The memory channels from processor socket 1 are identified as Channel A, B, C and D. The memory channels from processor socket 2 are identified as Channel E, F, G, and H.  Each memory slot on the server board is identified by channel and slot number within that channel. For example, DIMM_A1 is the first slot on Channel A on processor 1; DIMM_E1 is the first DIMM socket on Channel E on processor 2.  The memory slots associated with a given processor are unavailable if the corresponding processor socket is not populated.  A processor may be installed without populating the associated memory slots provided a second processor is installed with associated memory. In this case, the memory is shared by the processors. However, the platform suffers performance degradation and latency due to the remote memory.  Processor sockets are self-contained and autonomous. However, all memory subsystem support (such as Memory RAS, Error Management,) in the BIOS setup are applied commonly across processor sockets.  The BLUE memory slots on the server board identify the first memory slot for a given memory channel. DIMM population rules require that DIMMs within a channel be populated starting with the BLUE DIMM slot or DIMM farthest from the processor in a "fill-farthest" approach. In addition, when populating a Quad-rank DIMM with a Single- or Dual-rank DIMM in the same channel, the Quad-rank DIMM must be populated farthest from the processor. Note that Quad-rank DIMMs and UDIMMs are not allowed in three slots populated configurations. Intel MRC will check for correct DIMM placement. Revision 1.1 19 Intel order number G24881-004