Intel S2600GZ S2600GZ/GL - Page 140

DCU Data Prefetcher is normally

Page 140 highlights

Intel® Server Board S2600GZ/GL TPS BIOS Setup Utility Option Values: Enabled Disabled Help Text: [Enabled] - Fetches adjacent cache line (128 bytes) when required data is not currently in cache. [Disabled] - Only fetches cache line with data required by the processor (64 bytes). Comments: MLC Spatial Prefetcher is normally Enabled, for best efficiency in L2 Cache and Memory Channel use, but disabling it may improve performance for some processing loads and on certain benchmarks. Back to [Processor Configuration Screen] - [Advanced Screen] DCU Data Prefetcher Option Values: Enabled Disabled Help Text: The next cache line will be prefetched into L1 data cache from L2 or system memory during unused cycles if it sees that the processor core has accessed several bytes sequentially in a cache line as data. [Disabled] - Only fetches cache line with data required by the processor (64 bytes). Comments: DCU Data Prefetcher is normally Enabled, for best efficiency in L1 Data Cache and Memory Channel use, but disabling it may improve performance for some processing loads and on certain benchmarks. Back to Processor Configuration Screen] - [Advanced Screen] DCU Instruction Prefetcher Option Values: Enabled Disabled Help Text: The next cache line will be prefetched into L1 instruction cache from L2 or system memory during unused cycles if it sees that the processor core has accessed several bytes sequentially in a cache line as data. Comments: DCU Data Prefetcher is normally Enabled, for best efficiency in L1 I Cache and Memory Channel use, but disabling it may improve performance for some processing loads and on certain benchmarks. Back to [Processor Configuration Screen] - [Advanced Screen] Direct Cache Access (DCA) Revision 1.1 127 Intel order number G24881-004

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Intel® Server Board S2600GZ/GL TPS
BIOS Setup Utility
Revision 1.1
Intel order number G24881-004
127
Option Values:
Enabled
Disabled
Help Text:
[Enabled]
Fetches adjacent cache line (128 bytes) when required data is not
currently in cache.
[Disabled]
Only fetches cache line with data required by the processor (64
bytes).
Comments:
MLC Spatial Prefetcher is normally
Enabled
, for best efficiency in
L2 Cache and Memory Channel use, but disabling it may improve performance for some
processing loads and on certain benchmarks.
Back to [
Processor Configuration Screen
]
[
Advanced Screen
]
DCU Data Prefetcher
Option Values:
Enabled
Disabled
Help Text:
The next cache line will be prefetched into L1 data cache from L2 or system
memory during unused cycles if it sees that the processor core has accessed
several bytes sequentially in a cache line as data.
[Disabled]
Only fetches cache line with data required by the processor (64
bytes).
Comments:
DCU Data Prefetcher is normally
Enabled
, for best efficiency in
L1 Data Cache and Memory Channel use, but disabling it may improve performance for
some processing loads and on certain benchmarks.
Back to
Processor Configuration Screen
]
[
Advanced Screen
]
DCU Instruction Prefetcher
Option Values:
Enabled
Disabled
Help Text:
The next cache line will be prefetched into L1 instruction cache from L2 or
system memory during unused cycles if it sees that the processor core has
accessed several bytes sequentially in a cache line as data.
Comments:
DCU Data Prefetcher is normally
Enabled
, for best efficiency in
L1 I Cache and Memory Channel use, but disabling it may improve performance for
some processing loads and on certain benchmarks.
Back to [
Processor Configuration Screen
]
[
Advanced Screen
]
Direct Cache Access (DCA)