Intel S2600GZ S2600GZ/GL - Page 28

Intel® Server Board S2600GZ/GL TPS Product Architecture Overview Error Processor microcode update failed Severity Major System Action The BIOS detects the error condition and responds as follows: Logs the POST Error Code into the SEL. Displays "816x: Processor 0x unable to apply microcode update" message in the Error Manager or on the screen. Takes Major Error action. The system may continue to boot in a degraded state, depending on the setting of POST Error Pause in Setup, or may halt with the POST Error Code in the Error Manager waiting for operator intervention. 3.1.4 Processor Thermal Design Power (TDP) Support To allow optimal operation and long-term reliability of Intel processor-based systems, the processor must remain within the defined minimum and maximum case temperature (TCASE) specifications. Thermal solutions not designed to provide sufficient thermal capability may affect the long-term reliability of the processor and system. The server board is designed to support the Intel® Xeon® Processor E5-2600 product family TDP guidelines up to and including 135W. Disclaimer Note: Intel Corporation server boards contain a number of high-density VLSI and power delivery components that need adequate airflow to cool. Intel ensures through its own chassis development and testing that when Intel server building blocks are used together, the fully integrated system will meet the intended thermal requirements of these components. It is the responsibility of the system integrator who chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of airflow required for their specific application and environmental conditions. Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of their published operating or non-operating limits. 3.2 Processor Functions Overview With the release of the Intel® Xeon® processor E5-2600 product family, several key system components, including the CPU, Integrated Memory Controller (IMC), and Integrated IO Module (IIO), have been combined into a single processor package and feature per socket; two Intel® QuickPath Interconnect point-to-point links capable of up to 8.0 GT/s, up to 40 lanes of Gen 3 PCI Express* links capable of 8.0 GT/s, and 4 lanes of DMI2/PCI Express* Gen 2 interface with a peak transfer rate of 5.0 GT/s. The processor supports up to 46 bits of physical address space and 48-bit of virtual address space. The following sections will provide an overview of the key processor features and functions that help to define the architecture, performance and supported functionality of the server board. For more comprehensive processor specific information, refer to the Intel® Xeon® processor E52600 product family documents listed in the Reference Documents list. 3.2.1 Processor Core Features:  Up to 8 execution cores  Each core supports two threads (Intel® Hyper-Threading Technology), up to 16 threads per socket  46-bit physical addressing and 48-bit virtual addressing  1 GB large page support for server applications  A 32-KB instruction and 32-KB data first-level cache (L1) for each core  A 256-KB shared instruction/data mid-level (L2) cache for each core  Up to 20 MB last level cache (LLC): up to 2.5 MB per core instruction/data last level cache (LLC), shared among all cores Revision 1.1 15 Intel order number G24881-004