Intel S2600GZ S2600GZ/GL - Page 29

Product Architecture Overview Intel® Server Board S2600GZ/GL TPS 3.2.2 Supported Technologies:  Intel® Virtualization Technology (Intel® VT)  Intel® Virtualization Technology for Directed I/O (Intel® VT-d)  Intel® Virtualization Technology "Sandy Bridge" Processor Extensions  Intel® Trusted Execution Technology (Intel® TXT)  Intel® 64 Architecture  Intel® Streaming SIMD Extensions 4.1 (Intel® SSE4.1)  Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.2)  Intel® Advanced Vector Extensions (Intel® AVX)  Intel® Hyper-Threading Technology  Execute Disable Bit  Intel® Turbo Boost Technology  Intel® Intelligent Power Technology  Data Direct I/O (DDIO)  Enhanced Intel® SpeedStep Technology 3.2.3 Intel® QuickPath Interconnect The Intel® QuickPath Interconnect (QPI) is a high speed, packetized, point-to-point interconnect used in the processor. The narrow high-speed links stitch together processors in distributed shared memory and integrated I/O platform architecture. It offers much higher bandwidth with low latency. The Intel® QuickPath Interconnect has an efficient architecture allowing more interconnect performance to be achieved in real systems. It has a snoop protocol optimized for low latency and high scalability, as well as packet and lane structures enabling quick completions of transactions. Reliability, availability, and serviceability features (RAS) are built into the architecture. The physical connectivity of each interconnect link is made up of twenty differential signal pairs plus a differential forwarded clock. Each port supports a link pair consisting of two uni-directional links to complete the connection between two components. This supports traffic in both directions simultaneously. To facilitate flexibility and longevity, the interconnect is defined as having five layers: Physical, Link, Routing, Transport, and Protocol. The Intel® QuickPath Interconnect includes a cache coherency protocol to keep the distributed memory and caching structures coherent during system operation. It supports both low-latency source snooping and a scalable home snoop behavior. The coherency protocol provides for direct cache-to-cache transfers for optimal latency. 16 Revision 1.1 Intel order number G24881-004