Intel S2600CP Technical Product Specification - Page 168

Intel® Server System P4000CP Power System Options Intel® Server Board S2600CP and Server System P4000CP TPS Disabled 0.3V ≤ Hysterisis ≤ 1.0V In 1.0-2.0V input voltages range is required  1.0 V PS is enable d  2.0 V PS is disable d Enabled 0V 1.0 2.0 3.46V V V Figure 60. PSON# Required Signal Characteristic. 13.3.6.2 PWOK (Power OK) Output Signal PWOK is a power OK signal and will be pulled HIGH by the power supply to indicate that all the outputs are within the regulation limits of the power supply. When any output voltage falls below regulation limits or when AC power has been removed for a time sufficiently long so that power supply operation is no longer guaranteed, PWOK will be de-asserted to a LOW state. See Table 46 for a representation of the timing characteristics of PWOK. The start of the PWOK delay time shall inhibited as long as any power supply output is in current limit. Table 109. PWOK Signal Characteristics Signal Type PWOK = High PWOK = Low Logic level low voltage, Isink=400uA Logic level high voltage, Isource=200A Sink current, PWOK = low Source current, PWOK = high PWOK delay: Tpwok_on PWOK rise and fall time Power down delay: Tpwok_off Open collector/drain output from power supply. Pull-up to VSB located in the power supply. Power OK Power Not OK MIN MAX 0V 0.4V 2.4V 3.46V 400uA 2mA 100ms 1000ms 100sec 1ms 200msec A recommended implementation of the Power Ok circuits is shown below. Note: the Power Ok circuits should be compatible with 5V pull up resistor (>10k) and 3.3V pull up resistor (>6.8k). 152 Revision 1.2 Intel order number G26942-003