Intel S2600CP Technical Product Specification - Page 178

Intel® Server System P4000CP Power System Options Intel® Server Board S2600CP and Server System P4000CP TPS 13.4.2.10 DC/DC Converters Dynamic Loading The output voltages remains within limits specified in table above for the step loading and capacitive loading specified in the table below. The load transient repetition rate is only a test specification. The  step load may occur anywhere within the MIN load to the MAX load shown in Tables 143 and 144. Table 130. Transient Load Requirements Output + 3.3VDC + 5VDC +5Vsb Max  Step Load Size 5A 5A 0.5A Max Load Slew Rate 0.25 A/s 0.25 A/s 0.25A/s Test capacitive Load 250 F 400 F 20 F 13.4.2.11 DC/DC Converter Capacitive Loading The DC/DC converters is stable and meet all requirements with the following capacitive loading ranges. Minimum capacitive loading applies to static load only. Table 131. Capacitive Loading Conditions Converter output +3.3VDC +5VDC 5Vstby Min 250 400 20 Max 6800 4700 350 Units F F F 13.4.2.12 DC/DC Converters Closed Loop stability Each DC/DC converter is unconditionally stable under all line/load/transient load conditions including capacitive load ranges specified in Section 13.5.2.11. A minimum of: 45 degrees phase margin and -10dB-gain margin is required. The PDB provides proof of the unit's closed-loop stability with local sensing through the submission of Bode plots. Closed-loop stability must be ensured at the maximum and minimum loads as applicable. 13.4.2.13 Common Mode Noise The Common Mode noise on any output does not exceed 350mV pk-pk over the frequency band of 10Hz to 20MHz.  The measurement shall be made across a 100Ω resistor between each of DC outputs, including ground, at the DC power connector and chassis ground (power subsystem enclosure).  The test set-up shall use a FET probe such as Tektronix model P6046 or equivalent. 13.4.2.14 Ripple/Noise The maximum allowed ripple/noise output of each DC/DC Converter is defined in below Table 95. This is measured over a bandwidth of 0Hz to 20MHz at the PDB output connectors. A 10F tantalum capacitor in parallel with a 0.1F ceramic capacitor are placed at the point of measurement. 162 Revision 1.2 Intel order number G26942-003