Intel S2600CP Technical Product Specification - Page 77

Super I/O SIO, 1.3.1.2, Graphics Controller, 1.3.1.3, Remote Keyboard, Video, Mouse,

Page 77 highlights

Intel® Server Board S2600CP and Server System P4000CP TPS Intel® Server Board S2600CP and Intel® Server System P4000CP Platform Management  Multiple Serial Peripheral Interface (SPI) flash interfaces  NAND/Memory interface  Sixteen mailbox registers for communication between the BMC and host  LPC ROM interface  BMC watchdog timer capability  SD/MMC card controller with DMA support  LED support with programmable blink rate controls on GPIOs  Port 80h snooping capability  Secondary Service Processor (SSP), which provides the HW capability of offloading time critical processing tasks from the main ARM core. Emulex* Pilot III contains an integrated SIO, KVMS subsystem and graphics controller with the following features: 6.1.3.1.1 Super I/O (SIO) The BMC integrates a super I/O module with the following features:  Keyboard Style/BT interface for BMC support  Two Fully Functional Serial Ports, compatible with the 16C550  Serial IRQ Support  Up to 16 Shared GPIO available for host processor  Programmable Wake-up Event Support  Plug and Play Register Set  Power Supply Control 6.1.3.1.2 Graphics Controller The graphics controller provides the following features:  Integrated Graphics Core with 2D Hardware accelerator  High speed Integrated 24-bit RAMDAC DDR-2/3 memory interface with 16Mbytes of memory allocated and reported for graphics memory. 6.1.3.1.3 Remote Keyboard, Video, Mouse, and Storage (KVMS ) The Integrated BMC contains a remote KVMS subsystem with the following features:  USB 2.0 interface for Keyboard, Mouse and Remote storage such as CD/DVD ROM and floppy  USB 1.1/USB 2.0 interface for PS2 to USB bridging, remote Keyboard and Mouse  Hardware Based Video Compression and Redirection Logic  Supports both text and Graphics redirection  Hardware assisted Video redirection using the Frame Processing Engine  Direct interface to the Integrated Graphics Controller registers and Frame buffer  Hardware-based encryption engine Revision 1.2 61 Intel order number G26942-003

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Intel® Server Board S2600CP and Server System P4000CP TPS
Intel® Server Board S2600CP and Intel® Server System P4000CP Platform Management
Revision 1.2
Intel order number G26942-003
61
Multiple Serial Peripheral Interface (SPI) flash interfaces
NAND/Memory interface
Sixteen mailbox registers for communication between the BMC and host
LPC ROM interface
BMC watchdog timer capability
SD/MMC card controller with DMA support
LED support with programmable blink rate controls on GPIOs
Port 80h snooping capability
Secondary Service Processor (SSP), which provides the HW capability of offloading time
critical processing tasks from the main ARM core.
Emulex* Pilot III contains an integrated SIO, KVMS subsystem and graphics controller with the
following features:
6.1.3.1.1
Super I/O (SIO)
The BMC integrates a super I/O module with the following features:
Keyboard Style/BT interface for BMC support
Two Fully Functional Serial Ports, compatible with the 16C550
Serial IRQ Support
Up to 16 Shared GPIO available for host processor
Programmable Wake-up Event Support
Plug and Play Register Set
Power Supply Control
6.1.3.1.2
Graphics Controller
The graphics controller provides the following features:
Integrated Graphics Core with 2D Hardware accelerator
High speed Integrated 24-bit RAMDAC
DDR-2/3 memory interface with 16Mbytes of memory allocated and reported for
graphics memory.
6.1.3.1.3
Remote Keyboard, Video, Mouse, and Storage (KVMS )
The Integrated BMC contains a remote KVMS subsystem with the following features:
USB 2.0 interface for Keyboard, Mouse and Remote storage such as CD/DVD ROM and
floppy
USB 1.1/USB 2.0 interface for PS2 to USB bridging, remote Keyboard and Mouse
Hardware Based Video Compression and Redirection Logic
Supports both text and Graphics redirection
Hardware assisted Video redirection using the Frame Processing Engine
Direct interface to the Integrated Graphics Controller registers and Frame buffer
Hardware-based encryption engine