Intel S2600CP Technical Product Specification - Page 49

Intel® Server Board S2600CP and Server System P4000CP TPS Intel® Server Board S2600CP Functional Architecture  Per channel memory test and initialization engine can initialize DRAM to all logical zeros with valid ECC (with or without data scrambler) or a predefined test pattern  Isochronous access support for Quality of Service (QoS)  Minimum memory configuration: independent channel support with 1 DIMM populated  Integrated dual SMBus* master controllers  Command launch modes of 1n/2n  RAS Support: o Rank Level Sparing and Device Tagging o Demand and Patrol Scrubbing o DRAM Single Device Data Correction (SDDC) for any single x4 or x8 DRAM device. Independent channel mode supports x4 SDDC. x8 SDDC requires lockstep mode o Lockstep mode where channels 0 and 1 and channels 2 and 3 are operated in lockstep mode o Data scrambling with address to ease detection of write errors to an incorrect address. o Error reporting by Machine Check Architecture o Read Retry during CRC error handling checks by iMC o Channel mirroring within a socket  CPU1 Channel Mirror Pairs (A,B) and (C,D)  CPU2 Channel Mirror Pairs (E,F) and (G,H) o Error Containment Recovery  Improved Thermal Throttling with dynamic Closed Loop Thermal Throttling (CLTT)  Memory thermal monitoring support for DIMM temperature 4.2.2.1 Supported Memory Table 4. UDIMM Support Ranks Per DIMM and Data Width Memory Capacity Per DIMM SRx8 NonECC DRx8 NonECC SRx16 NonECC 1GB 2GB 512MB 2GB 4GB 1GB 4GB 8GB 2GB Speed (MT/s) and Voltage Validated by Slot per Channel (SPC) and DIMM Per Channel (DPC) Intel® Server Board S2600CP (2 Slots per Channel) 1DPC 2DPC 1.35V 1.5V 1.35V 1.5V n/a 1066, 1333 n/a 1066, 1333 n/a 1066, 1333 n/a 1066, 1333 n/a 1066, 1333 n/a 1066, 1333 SRx8 ECC 1GB 2GB 4GB 1066, 1333 1066, 1333 1066 1066, 1333 DRx8 ECC 2GB 4GB 8GB 1066, 1333 1066, 1333 1066 1066, 1333 Revision 1.2 33 Intel order number G26942-003