Intel SE7525GP2 Product Specification - Page 147
POST Code Checkpoints
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Intel® Server Boards SE7320SP2 and SE7525GP2 Error Reporting and Handling 6.3.3 POST Code Checkpoints Table 65. POST Code Checkpoints Checkpoint 03 04 05 06 08 C0 C1 C2 C5 C6 C7 0A 0B 0C 0E 13 24 30 2A Diagnostic LED Decoder G=Green, R=Red, A=Amber MSB LSB OFF OFF G G OFF G OFF OFF OFF G OFF G OFF G G OFF G OFF OFF OFF R R OFF OFF R R OFF G R R G OFF R A OFF G R A G OFF R A G G G OFF G OFF G OFF G G G G OFF OFF G G G OFF OFF OFF OFF OFF G G R OFF R G OFF A A OFF R OFF Description Disable NMI, parity, video for EGA, and DMA controllers. Initialize BIOS, POST, Run-time data area. Initialize BIOS modules on POST entry and GPNV area. Initialized CMOS as mentioned in the Kernel Variable "wCMOSFlags." Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is OK. Verify CMOS checksum manually by reading storage area. If the CMOS checksum is bad, update CMOS with power-on default values and clear passwords. Initialize status register A. Initializes data variables that are based on CMOS setup questions. Initializes both the 8259 compatible PICs in the system Initializes the interrupt controlling hardware (generally PIC) and interrupt vector table. Do R/W test to CH-2 count reg. Initialize CH-0 as system timer. Install the POSTINT1Ch handler. Enable IRQ-0 in PIC for system timer interrupt. Traps INT1Ch vector to "POSTINT1ChHandlerBlock." Initializes the CPU. The BAT test is being done on KBC. Program the keyboard controller command byte is being done after Auto detection of KB/MS using AMI KB-5. Early CPU Init Start -- Disable Cache - Init Local APIC Set up boot strap processor Information Set up boot strap processor for POST Enumerate and set up application processors Re-enable cache for boot strap processor Early CPU Init Exit Initializes the 8042 compatible Key Board controller. Detects the presence of PS/2 mouse. Detects the presence of Keyboard in KBC port. Testing and initialization of different Input Devices. Also, update the Kernel Variables. Traps the INT09h vector, so that the POST INT09h handler gets control for IRQ1. Uncompress all available language, BIOS logo, and Silent logo modules. Early POST initialization of chipset registers. Uncompress and initialize any platform specific BIOS modules. Initialize System Management Interrupt. Initializes different devices through DIM. See DIM Code Checkpoints section of document for more information. Revision 4.0 135