Intel SE7525GP2 Product Specification - Page 61
System Management Mode Handling
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Intel® Server Boards SE7320SP2 and SE7525GP2 Functional Architecture 3.7.1.4 System Management Mode Handling The chipset supports System Management Mode (SMM) operation in one of three modes. System Management RAM (SMRAM) provides code and data storage space for the SMI_L handler code, and is made visible to the processor only on entry to SMM, or other conditions which can be configured using the Intel chipset. The MCH supports three SMM options: Compatible SMRAM (C_SMRAM) High segment (HSEG) Top of memory segment (TSEG) Three abbreviations are used later in the table that describes SMM Space Transaction Handling. SMM Space Enabled Compatible (C) High (H) TSEG (T) Transaction Address Space (Adr) A0000h to BFFFFh 0FEDA0000h TO 0FEDBFFFFh (TOLM-TSEG_SZ) to TOLM DRAM Space (DRAM) A0000h to BFFFFh A0000h to BFFFFh (TOLM-TSEG_SZ) to TOLM Notes: High SMM is different than in previous chipsets. In previous chipsets the high segment was the 384 KB region from A_0000h to F_FFFFh. However C_0000h to F_FFFFh was not useful so it is deleted in MCH. TSEG SMM is different than in previous chipset. In previous chipsets the TSEG address space was offset by 256 MB to allow for simpler decoding and the TSEG was remapped to directly under the TOLM. In the MCH the TSEG region is not offset by 256 MB and it is not remapped. Table 17. SMM Space Table Global Enable G_SMRAME 0 1 1 1 1 High Enable H_SMRAME X 0 0 1 1 TSEG Enable TSEG_EN X 0 1 0 1 Compatible (C) Range Disable Enable Enable Disable Disable High (H) Range Disable Disable Disable Enable Enable TSEG (T) Range Disable Disable Enable Disable Enable Revision 4.0 49