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Intel SE7525GP2 Product Specification - Page 157

Intel® Server Boards SE7320SP2 and SE7525GP2, Connector Definitions and Pin-outs, Revision 4.0

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Intel® Server Boards SE7320SP2 and SE7525GP2 Connector Definitions and Pin-outs Pin No Pin Name C4 VCC C5 VTT C6 RSP# C7 VSS C8 A35# C9 A34# C10 VTT C11 A30# C12 A23# C13 VSS C14 A16# C15 A15# C16 VCC C17 A8# C18 A6# C19 VSS C20 REQ3# C21 REQ2# C22 VCC C23 DEFER# C24 TDI C25 VSS C26 IGNNE# C27 SMI# C28 VCC C29 VSS C30 VCC C31 VSS D1 VCC D2 VSS D3 VID2 D4 STPCLK# D5 VSS D6 INIT# D7 MCERR# D8 VCC D9 AP1# D10 BR3# 1 D11 VSS D12 A29# D13 A25# Pin No Pin Name G1 VSS G2 VCC G3 VSS G4 VCC G5 VSS G6 VCC G7 BOOT_SELEC T G8 VCC G9 VSS G23 LINT1 G24 VCC G25 VSS G26 VCC G27 VSS G28 VCC G29 VSS G30 VCC G31 VSS H1 VCC H2 VSS H3 VCC H4 VSS H5 VCC H6 VSS H7 VCC H8 VSS H9 VCC H23 VCC H24 VSS H25 VCC H26 VSS H27 VCC H28 VSS H29 VCC H30 VSS H31 VCC J1 VSS J2 VCC J3 VSS J4 VCC J5 VSS Pin No Pin Name Pin No Pin Name Pin No Pin Name N27 VCC Y9 D62# AD6 VCC N28 VSS Y10 VTT AD7 D57# N29 VCC Y11 DSTBP3# AD8 D46# N30 VSS Y12 DSTBN3# AD9 VSS N31 VCC Y13 VSS AD10 D45# P1 VSS Y14 DSTBP2# AD11 D40# P2 VCC Y15 DSTBN2# AD12 VTT P3 VSS P4 VCC P5 VSS P6 VCC P7 VSS P8 VCC P9 VSS P23 VSS P24 VCC P25 VSS P26 VCC P27 VSS P28 VCC P29 VSS P30 VCC P31 VSS R1 VCC R2 VSS R3 VCC R4 VSS R5 VCC R6 VSS R7 VCC R8 VSS R9 VCC R23 VCC R24 VSS R25 VCC R26 VSS R27 VCC R28 VSS R29 VCC R30 VSS R31 VCC Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30 Y31 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA1 VCC AD13 DSTBP1# AD14 DSTBN1# AD15 VSS AD16 DSTBP0# AD17 DSTBN0# AD18 VCC AD19 D5# AD20 D2# AD21 VSS AD22 D0# AD23 THERMDA AD24 THERMDC AD25 NC AD26 VCC AD27 VSS AD28 VCC AD29 VSS AD30 BSEL0 2 AD31 VCC AE2 VSSA AE3 VCC AE4 TESTHI4 AE5 D61# AE6 VSS AE7 D54# AE8 D53# AE9 VTT AE10 D48# AE11 D49# AE12 VSS AE13 D33# VSS D24# AE14 AE15 AE16 D38# D39# VSS COMP0 VSS D36# D30# VCC D29# DBI1# VSS D21# D18# VCC D4# NC NC VCC VSS VSS VCC SMB_PRT TESTHI6 SLP# D58# VCC D44# D42# VSS DBI2# D35# VCC Reserved Reserved Revision 4.0 145

Section	Page
1. Introduction	13
1.1 Chapter Outline	13
1.2 Server Board Use Disclaimer	13
2. Server Board Overview	14
2.1 Intel® Server Board SE7320SP2	14
2.1.1 Intel® Server Board SE7320SP2 Feature Set	14
2.2 Intel® Server Board SE7525GP2	16
2.2.1 Intel® Server Board SE7525GP2 Feature Set	16
3. Functional Architecture	20
3.1 Processor Sub-system	21
3.1.1 Processor Voltage Regulator Devices (VRDs)	22
3.1.2 Reset Configuration Logic	22
3.1.3 Processor Module Presence Detection	22
3.1.4 GTL2006	22
3.1.5 Common Enabling Kit (CEK) Design Support	23
3.1.6 Processor Support	24
3.1.6.1 Processor Mis-population Detection	24
3.1.6.2 Mixed Processor Steppings	25
3.1.6.3 Mixed Processor Models	25
3.1.6.4 Mixed Processor Families	25
3.1.6.5 Mixed Processor Cache Sizes	25
3.1.6.6 Jumperless Processor Speed Settings	25
3.1.6.7 Microcode	25
3.1.6.8 Processor Cache	25
3.1.6.9 Hyper-Threading Technology	26
3.1.6.10 Intel SpeedStep® Technology	26
3.1.6.11 Intel® Extended Memory 64 Technology (Intel® EM64T) Support	26
3.1.6.12 Execute Disable Bit support	26
3.1.7 Multiple Processor Initialization	26
3.1.8 CPU Thermal Sensors	27
3.1.9 Processor Thermal Control Sensor	27
3.1.10 Processor Thermal Trip Shutdown	27
3.1.11 Processor IERR	27
3.2 Intel® E7320 Chipset (Intel® Server Board SE7320SP2)	27
3.2.1 Memory Controller Hub (MCH)	28
3.2.1.1 Front Side Bus (FSB)	28
3.2.1.2 MCH Memory Sub-System Overview	28
3.2.1.3 PCI Express*	29
3.2.1.4 Hub Interface	29
3.3 Intel® E7525 Chipset (Intel® Server Board SE7525GP2)	29
3.3.1 Memory Controller Hub (MCH)	30
3.3.1.1 Front Side Bus (FSB)	30
3.3.1.2 MCH Memory Sub-System Overview	30
3.3.1.3 PCI Express*	31
3.3.1.4 Hub Interface	31
3.4 Intel® 6300ESB ICH	31
3.4.1 PCI Interface	32
3.4.2 IDE Interface (Bus Master Capability and Synchronous DMA Mode)	32
3.4.3 SATA Controller	32
3.4.4 Low Pin Count (LPC) Interface	32
3.4.5 Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller)	32
3.4.6 Advanced Programmable Interrupt Controller (APIC)	33
3.4.7 Universal Serial Bus (USB) Controller	33
3.4.8 RTC	33
3.4.9 GPIO	33
3.4.10 Enhanced Power Management	34
3.4.11 System Management Bus (SMBus 2.0)	34
3.5 Memory Sub-System	34
3.5.1 Memory Sizing	34
3.5.2 Memory Population	35
3.5.3 I2C Bus	37
3.5.4 Disabling DIMMs	38
3.5.4.1 Mechanism for CME/SEC Counter	38
3.5.5 Memory RASUM Features	39
3.5.5.1 DRAM ECC – Intel® x4 Single Device Data Correction (x4 SDDC)	40
3.5.5.2 Integrated Memory Scrub Engine	40
3.5.5.3 Retry on Uncorrectable Error	40
3.5.5.4 Integrated Memory Initialization Engine	41
3.5.5.5 DIMM Sparing Function	41
3.6 I/O Sub-System	42
3.6.1 PCI Subsystem	42
3.6.1.1 P32-A: 32-bit, 33-MHz PCI Subsystem	42
3.6.1.2 P64-A: 64-bit, 66 MHz PCI Subsystem	43
3.6.1.3 P64-Express4: x4 PCI Express* Bus Segment	43
3.6.1.4 P64-Express16: x16 PCI Express bus segment	43
3.6.1.5 Scan Order	43
3.6.1.6 Resource Assignment	43
3.6.1.7 Automatic IRQ Assignment	43
3.6.1.8 Option ROM Support	43
3.6.1.9 PCI APIs	44
3.6.2 Split Option ROM	44
3.6.3 Interrupt Routing	44
3.6.3.1 Legacy Interrupt Routing	44
3.6.3.2 APIC Interrupt Routing	44
3.6.3.3 Legacy Interrupt Sources	45
3.6.3.4 Serialized IRQ Support	45
3.6.3.5 IRQ Scan for PCI IRQ	45
3.6.4 IDE Support	48
3.6.4.1 Ultra ATA/100	48
3.6.4.2 IDE Initialization	48
3.6.5 SATA Support	48
3.6.5.1 SATA RAID	49
3.6.5.2 Intel® RAID Technology Option ROM	49
3.6.6 Video Controller	49
3.6.6.1 Video Modes	50
3.6.6.2 Video Memory Interface	50
3.6.7 Network Interface Controller (NIC)	51
3.6.7.1 Intel® 82541	51
3.6.7.2 NIC Connector and Status LEDs	51
3.6.8 USB 2.0 Support	52
3.6.9 Super I/O Chip	52
3.6.9.1 GPIOs	53
3.6.9.2 Serial Ports	54
3.6.9.3 Floppy Disk Controller	54
3.6.9.4 Keyboard and Mouse	54
3.6.9.5 Wake-up Control	54
3.6.10 BIOS Flash	55
3.7 Configuration and Initialization	55
3.7.1 Memory Space	55
3.7.1.1 DOS Compatibility Region	57
3.7.1.2 Extended Memory	59
3.7.1.3 Memory Shadowing	60
3.7.1.4 System Management Mode Handling	61
3.7.2 I/O Map	62
3.7.3 Accessing Configuration Space	64
3.7.3.1 CONFIG_ADDRESS Register	65
3.7.3.1.1 Bus Number	65
3.7.3.1.2 Device Number and IDSEL Mapping	65
3.8 Clock Generation and Distribution	67
3.8.1 Real Time Clock	67
4. System BIOS	68
4.1 BIOS Identification String	68
4.2 BIOS POST Splash Screen	69
4.2.1 User Interface	69
4.2.1.1 System State Window	70
4.2.1.2 Logo/Diagnostic Window	70
4.2.1.3 Current Activity Window	70
4.2.1.4 System Diagnostic Screen	70
4.2.1.5 Static Information Display	70
4.2.1.5.1 Quiet Boot / OEM Splash Screen	71
4.2.1.5.2 BIOS Boot Popup Menu	71
4.3 BIOS Setup Utility	72
4.3.1 Localization	72
4.3.2 Console Redirection	72
4.3.3 Configuration Reset	72
4.3.4 Keyboard Commands	73
4.4 Entering BIOS Setup	74
4.4.1 Main Menu	74
4.4.2 Advanced Menu	75
4.4.2.1 Processor Configuration Sub-menu	75
4.4.2.2 IDE Configuration Sub-menu	77
4.4.2.3 Floppy Configuration Sub-menu	80
4.4.2.4 Super I/O Configuration Sub-menu	81
4.4.2.5 USB Configuration Sub-menu	81
4.4.2.6 USB Mass Storage Device Configuration Sub-menu	82
4.4.2.7 PCI Configuration Sub-menu	83
4.4.2.8 Memory Configuration Sub-menu	84
4.4.3 Boot Menu	85
4.4.3.1 Boot Settings Configuration Sub-menu Selections	85
4.4.3.2 Boot Device Priority Sub-menu Selections	86
4.4.3.2.1 Hard Disk Drive Sub-menu Selections	86
4.4.3.2.2 Removable Drive Sub-menu Selections	86
4.4.3.2.3 ATAPI CD-ROM Drives Sub-menu Selections	87
4.4.4 Security Menu	87
4.4.5 Server Menu	88
4.4.5.1 System Management Sub-menu Selections	90
4.4.5.2 Power Management Features Sub-menu Selections	90
4.4.5.3 Serial Console Features Sub-menu Selections	91
4.4.5.4 Event Log Configuration Sub-menu Selections	92
4.4.6 Exit Menu	93
4.5 Flash Update Utility	93
4.6 Rolling BIOS and On-line Updates	93
4.7 Flash Update Utility	94
4.7.1 Flash BIOS	94
4.7.1.1 Updating the BIOS from DOS	95
4.7.1.2 Updating the BIOS from Microsoft* Windows* 2000/2003/XP	95
4.7.1.3 Updating the BIOS from Linux	95
4.7.1.4 Updating the BIOS from the EFI Shell	96
4.7.2 User Binary Area	96
4.7.3 Recovery Mode	96
4.7.3.1 BIOS Recovery	97
4.7.3.2 Multi-disk Recovery	98
4.7.4 Update OEM Logo	98
4.7.4.1 Changing the OEM Logo for DOS	99
4.7.4.2 Changing the OEM Logo for Microsoft Windows* 2000 / 2003 / XP	99
4.8 OEM Binary	100
4.9 Operating System Boot, Sleep, and Wake	101
4.9.1 Microsoft Windows* Compatibility	101
4.9.2 Advanced Configuration and Power Interface (ACPI)	101
4.9.3 Sleep and Wake Functionality	102
4.9.4 Power Switch Off to On	102
4.9.5 On to Off (OS absent)	103
4.9.6 On to Off (OS present)	103
4.9.7 System Sleep States	103
4.10 Security	104
4.10.1 Operating Model	105
4.10.2 Administrator/User Passwords and F2 Setup Usage Model	105
4.10.3 Password Clear Jumper	107
4.11 Extensible Firmware Interface (EFI)	107
4.11.1 EFI Shell	107
5. Platform Management	107
5.1.1 5V Standby	109
5.1.2 IPMI Messaging, Commands, and Abstractions	109
5.1.3 IPMI Sensor Model	110
5.1.4 Private Management Buses	110
5.1.5 Mini-Baseboard Management Controller	111
5.2 Onboard Platform Instrumentation Features and Functionality	113
5.2.1 mBMC Self-test	114
5.2.2 SMBus Interfaces	114
5.2.3 External Interface to mBMC	114
5.2.3.1 Private Management I2C Buses	115
5.2.4 Messaging Interfaces	115
5.2.4.1 Channel Management	115
5.2.4.2 User Model	115
5.2.4.3 Request/Response Protocol	115
5.2.4.4 Host to mBMC Communication Interface	116
5.2.4.5 LAN Interface	116
5.2.5 Direct Platform Control (IPMI over LAN)	117
5.2.5.1 LAN Channel Specifications	118
5.2.5.2 LAN Drivers and Setup	119
5.2.5.3 BIOS Boot Flags	119
5.2.5.4 Boot Flags and LAN Console Redirection	119
5.2.6 Wake On LAN / Power On LAN and Magic Packet Support	119
5.2.6.1 Wake On LAN in S4/S5	119
5.2.7 Watchdog Timer	120
5.2.8 System Event Log (SEL)	120
5.2.8.1 Timestamp Clock	120
5.2.9 Sensor Data Record (SDR) Repository	121
5.2.9.1 Initialization Agent	121
5.2.10 Event Message Reception	121
5.2.11 Event Filtering and Alerting	121
5.2.11.1 Platform Event Filtering (PEF)	121
5.2.11.2 Alert over LAN	123
5.2.11.3 System Identification in Alerts	123
5.2.11.4 Platform Alerting Setup	123
5.2.11.5 Alerting On Power Down Events	124
5.2.11.6 Alerting On System Reset Events	124
5.2.11.7 Alert-in-Progress Termination	124
5.2.12 NMI Generation	124
5.2.13 SMI Generation	125
5.3 Platform Management Interconnects	125
5.3.1 Power Supply Interface Signals	125
5.3.1.1 Power-up Sequence	126
5.3.1.2 Power-down Sequence	126
5.3.1.3 Power Control Sources	126
5.3.2 System Reset Control	127
5.3.2.1 Reset Signal Output	127
5.3.2.2 Reset Control Sources	127
5.3.3 Temperature-based Fan Speed Control	127
5.3.3.1 Fan Kick-start	128
5.3.4 Front Panel Control	128
5.3.4.1 Power Button	128
5.3.4.2 Reset Button	129
5.3.4.3 Diagnostic Interrupt Button (Front Panel NMI)	129
5.3.4.4 Chassis ID Button and LED	129
5.3.4.5 Status/Fault LED	130
5.3.4.6 Chassis Intrusion Switch	131
5.3.4.7 Front Panel Lockout	131
5.3.5 Secure Mode Operation	131
5.3.6 FRU Information	132
5.3.6.1 mBMC FRU Inventory Area Format	132
5.4 Sensors	133
5.4.1 Sensor Type Codes	133
6. Error Reporting and Handling	138
6.1 Error Logging	138
6.1.1 Error Sources and Types	138
6.1.2 SMI Handler	138
6.1.2.1 PCI Bus Error	138
6.1.2.2 Processor Bus Error	139
6.1.2.3 Memory Bus Error	139
6.1.2.4 System Limit Error	139
6.1.2.5 Processor Failure	139
6.1.2.6 Boot Event	140
6.1.2.7 Logging Format Conventions	140
6.1.3 Single-bit ECC Error Throttling Prevention	140
6.2 Error Messages and Error Codes	141
6.2.1 POST Error Codes and Messages	141
6.2.2 Boot Block Error Beep Codes	144
6.2.3 POST Error Beep Codes	144
6.2.3.1 Troubleshooting BIOS Beep Codes	144
6.2.4 \	145
6.3 Checkpoints	145
6.3.1 System ROM BIOS POST Task Test Point (Port 80h Code)	145
6.3.2 Diagnostic LEDs	145
6.3.3 POST Code Checkpoints	147
6.3.4 Bootblock Initialization Code Checkpoints	149
6.3.5 Bootblock Recovery Code Checkpoint	150
6.3.6 DIM Code Checkpoints	151
6.3.7 ACPI Runtime Checkpoints	151
6.3.8 Memory Error Codes	152
6.4 Intel® Light-Guided Diagnostics	152
7. Connector Definitions and Pin-outs	153
7.1 Main Power Connector	153
7.2 Memory Module Connector	154
7.3 Processor Socket	155
7.4 I2C Headers	158
7.5 PCI Slot Connector	159
7.6 Front Panel Connector	163
7.7 VGA Connector	164
7.8 NIC Connector	164
7.9 IDE Connector	165
7.10 SATA Connectors	165
7.11 USB Connector	166
7.12 Floppy Connector	167
7.13 Serial Port Connector	168
7.14 Keyboard and Mouse Connector	169
7.15 Miscellaneous Headers	169
7.15.1 Fan Header	169
7.15.2 Intrusion Cable Connector	170
7.15.3 SCSI LED Header	170
7.16 Configuration Jumpers	171
7.16.1 System Recovery and Update Jumpers	171
7.16.2 Rolling BIOS Bank Selection Jumper	172
8. General Specifications	173
8.1 Absolute Maximum Ratings	173
8.2 Mean Time Between Failure (MTBF)	173
8.3 Processor Power Support	174
8.4 Power Supply Specifications	174
8.4.1 Power Timing	174
8.4.2 Voltage Recovery Timing Specifications	178
9. Product Regulatory Compliance	179
9.1 Product Safety Compliance	179
9.1.1 Product EMC Compliance	179
9.1.2 Mandatory/Standard: Certifications, Registration, Declarations	180
9.1.3 Product Regulatory Compliance Markings	180
9.2 Electromagnetic Compatibility Notices	180
9.2.1 Europe (CE Declaration of Conformity)	180
9.2.2 Australian Communications Authority (ACA) (C-Tick Declaration of Conformity)	180
9.2.3 Ministry of Economic Development (New Zealand) Declaration of Conformity	181
9.2.4 BSMI (Taiwan)	181

Match case Limit results 1 per page

Intel® Server Boards SE7320SP2 and SE7525GP2

Connector Definitions and Pin-outs

Revision 4.0

145

Pin No

Pin Name

Pin No

Pin Name

Pin No

Pin Name

Pin No

Pin Name

Pin No

Pin Name

VCC

VSS

N27

VCC

D62#

AD6

VCC

VTT

VCC

N28

VSS

Y10

VTT

AD7

D57#

RSP#

VSS

N29

VCC

Y11

DSTBP3#

AD8

D46#

VSS

VCC

N30

VSS

Y12

DSTBN3#

AD9

VSS

A35#

VSS

N31

VCC

Y13

VSS

AD10

D45#

A34#

VCC

VSS

Y14

DSTBP2#

AD11

D40#

C10

VTT

BOOT_SELEC

VCC

Y15

DSTBN2#

AD12

VTT

C11

A30#

VCC

VSS

Y16

VCC

AD13

D38#

C12

A23#

VSS

VCC

Y17

DSTBP1#

AD14

D39#

C13

VSS

G23

LINT1

VSS

Y18

DSTBN1#

AD15

VSS

C14

A16#

G24

VCC

Y19

VSS

AD16

COMP0

C15

A15#

G25

VSS

Y20

DSTBP0#

AD17

VSS

C16

VCC

G26

VCC

Y21

DSTBN0#

AD18

D36#

C17

A8#

G27

VSS

Y22

VCC

AD19

D30#

C18

A6#

G28

VCC

P23

VSS

Y23

D5#

AD20

VCC

C19

VSS

G29

VSS

P24

VCC

Y24

D2#

AD21

D29#

C20

REQ3#

G30

VCC

P25

VSS

Y25

VSS

AD22

DBI1#

C21

REQ2#

G31

VSS

P26

VCC

Y26

D0#

AD23

VSS

C22

VCC

P27

VSS

Y27

THERMDA AD24

D21#

C23

DEFER#

VSS

P28

VCC

Y28

THERMDC AD25

D18#

C24

TDI

VCC

P29

VSS

Y29

AD26

VCC

C25

VSS

P30

VCC

Y30

VCC

AD27

D4#

C26

IGNNE#

VCC

P31

VSS

Y31

VSS

AD28

C27

SMI#

VSS

VCC

AA1

VCC

AD29

C28

VCC

VSS

AA2

VSS

AD30

VCC

C29

VSS

VCC

AA3

BSEL0

AD31

VSS

C30

VCC

VSS

AA4

VCC

AE2

VSS

C31

VSS

H23

VCC

AA5

VSSA

AE3

VCC

H24

VSS

AA6

VCC

AE4

SMB_PRT

VSS

H25

VCC

AA7

TESTHI4

AE5

TESTHI6

VID2

H26

VSS

AA8

D61#

AE6

SLP#

STPCLK#

H27

VCC

AA9

VSS

AE7

D58#

VSS

H28

VSS

R23

VCC

AA10

D54#

AE8

VCC

INIT#

H29

VCC

R24

VSS

AA11

D53#

AE9

D44#

MCERR#

H30

VSS

R25

VCC

AA12

VTT

AE10

D42#

VCC

H31

VCC

R26

VSS

AA13

D48#

AE11

VSS

AP1#

VSS

R27

VCC

AA14

D49#

AE12

DBI2#

D10

BR3#

VCC

R28

VSS

AA15

VSS

AE13

D35#

D11

VSS

R29

VCC

AA16

D33#

AE14

VCC

D12

A29#

VCC

R30

VSS

AA17

VSS

AE15

Reserved

D13

A25#

VSS

R31

VCC

AA1

D24#

AE16

Reserved