Intel SE7525GP2 Product Specification - Page 25
Mixed Processor Cache Sizes
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Intel® Server Boards SE7320SP2 and SE7525GP2 Functional Architecture 3.1.6.2 Mixed Processor Steppings For optimum system performance, only identical processors should be installed in a system. Processor steppings within a common processor family can be mixed in a system provided that there is no more than a one stepping difference between them. If the installed processors are more than one stepping apart, an error is reported. Acceptable mixed steppings are not reported as errors by the BIOS. 3.1.6.3 Mixed Processor Models Processor models cannot be mixed in a system. If this condition is detected, error 8196 is logged in the SEL. 3.1.6.4 Mixed Processor Families Processor families cannot be mixed in a system. If this condition is detected, error 8194 is logged in the SEL. 3.1.6.5 Mixed Processor Cache Sizes If the installed processors have mixed cache sizes, error 8192 will be logged in the SEL. The size of all cache levels must match between all installed processors. Mixed cache processors are not supported. 3.1.6.6 Jumperless Processor Speed Settings The Intel® Xeon® processor does not utilize jumpers or switches to set the processor frequency. The BIOS reads the highest ratio register from all processors in the system. If all processors are the same speed, the Actual Ratio register is programmed with the value read from the High Ratio register. If all processors do not match, the highest common value between High and Low Ratio is determined and programmed to all processors. If there is no value that works for all installed processors, all processors not capable of speeds supported by the boot strap processor (BSP) are disabled and an error is displayed. 3.1.6.7 Microcode IA-32 processors have the capability of correcting specific errata through the loading of an Intel supplied data block, i.e., microcode update. The BIOS is responsible for storing the update in non-volatile memory and loading it into each processor during POST. The BIOS allows a number of microcode updates to be stored in the flash, limited by the amount of free space available. The BIOS supports variable size microcode updates. The BIOS verifies the signature prior to storing the update in the flash. 3.1.6.8 Processor Cache The BIOS enables all levels of processor cache as early as possible during POST. There are no user options to modify the cache configuration, size or policies. The largest and highest level cache detected is reported in the BIOS Setup. Revision 4.0 13