Intel SE7525GP2 Product Specification - Page 31
Intel, 6300ESB ICH
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Intel® Server Boards SE7320SP2 and SE7525GP2 Functional Architecture 3.3.1.3 PCI Express* The Intel® E7525 MCH is part of the first family of Intel chipsets to support the PCI Express* high speed serial I/O interface for high I/O bandwidth. The Intel E7525 MCH implementation of the scalable PCI Express interface complies with the PCI Express Interface Specification, Rev 1.0a. The MCH provides one x16 and one configurable x8 PCI Express interface with a maximum theoretical bandwidth of 4 GB/s. The x8 PCI Express interface may alternatively be configured (bifurcated) as two independent x4 PCI Express interfaces. On the Server Board SE7525GP2, the PCI Express bandwidth is implemented as one x16 slot for high bandwidth PCI Express graphics adapters and one x4 slot for PCI Express add-in cards. The Intel® E7525 MCH is a root-class component as defined in the PCI Express Interface Specification, Rev 1.0a. The PCI Express interfaces of the MCH support connection to a variety of bridges and devices compliant with the same revision of the specification. See the SE7320SP2 / SE7525GP2 Tested Hardware and OS List for the add-in cards tested on this platform. 3.3.1.4 Hub Interface The MCH interfaces with the Intel® 6300ESB I/O controller hub via a dedicated hub Interface supporting a peak bandwidth of 266 MB/s using a x4 base clock of 66 MHz. 3.4 Intel® 6300ESB ICH The Intel® 6300ESB is a multi-function device that provides an upstream hub interface for access to several embedded I/O functions and features including: PCI Local Bus Specification, Revision 2.3 with support for 33 MHz PCI operations. PCI-X 2.2 specification support for up to PCI-X 66 MHz operation ACPI power management logic support Enhanced DMA controller, interrupt controller, and timer functions Integrated IDE controller with support for Ultra ATA100/66/33 Integrated SATA controller USB host interface with support for four USB ports; four UHCI host controllers; one EHCI high-speed USB 2.0 host controller System Management Bus (SMBus) Specification, Version 2.0 with additional support for I2C devices Low pin count (LPC) interface Firmware hub (FWH) interface support Each function within the Intel® 6300ESB I/O controller has its own set of configuration registers. Once configured, each appears to the system as a distinct hardware controller sharing the same PCI bus interface. Revision 4.0 19