Intel SE7525GP2 Product Specification - Page 76
System BIOS, Intel® Server Boards SE7320SP2 and SE7525GP2, Revision 4.0
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System BIOS Intel® Server Boards SE7320SP2 and SE7525GP2 Feature Cache L3 Max CPUID Value Limit Options N/A Disabled Enabled Hyper-Threading Technology Disabled Enabled HT Technology in MPS Disabled Enabled Intel® SpeedStep™ Tech. Disabled Auto Execute Disable Bit Hardware Prefetcher Disabled Enabled Disabled Enabled Adjacent Cache Line Prefetch Disabled Enabled Help Text N/A This should be enabled in order to boot legacy OSes that cannot support processors with extended CPUID functions. Enable Hyper-Threading Technology only if OS supports it. Enabling adds secondary processor threads to the MPS Table for pre-ACPI OSes. Only enable this feature if the pre-ACPI OS supports Hyper-Threading Technology Select disabled for maximum CPU speed. Select enabled to allow the OS to reduce power consumption. Intel's Execute Disable Bit functionality can prevent certain virus attacks This should be enabled in order to enable or disable the Hardware Prefetcher Disable feature This should be enabled in order to enable or disable the Adjacent Cache Line Prefetch Disable Feature Description Displays cache L3 size. Visible only if the processor contains an L3 cache. Controls Hyper-Threading state. Primarily used to support older operating systems that do not support Hyper Threading. Visible only if the processor has this feature. Visible only if the processor has this feature. 64 Revision 4.0