Intel SE7525GP2 Product Specification - Page 64
Accessing Configuration Space
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Functional Architecture Intel® Server Boards SE7320SP2 and SE7525GP2 Address (es) 03E8h - 03Efh 03F0h - 03F5h 03F6h - 03F7h 03F8h - 03FFh 0400h - 043Fh 0461h 0480h - 048Fh 04C0h - 04CFh 04D0h - 04D1h 04D4h - 04D7h 04D8h - 04DFh 04E0h - 04FFh 051Ch 0678h - 067Ah 0778h - 077Ah 07BCh - 07Beh 0CF8h 0CF9h 0CFCh Serial Port A Resource Floppy Disk Controller Primary IDE - Sec Floppy Serial Port A (primary) DMA Controller 1, Extended Mode Registers Extended NMI / Reset Control DMA High Page Register DMA Controller 2, High Base Register Interrupt Controllers 1 and 2 Control Register DMA Controller 2, Extended Mode Register Reserved DMA Channel Stop Registers Software NMI (051Ch) Parallel Port (ECP) Parallel Port (ECP) Parallel Port (ECP) PCI CONFIG_ADDRESS Register Intel® Server Board SE7320SP2 Turbo and Reset Control PCI CONFIG_DATA Register Notes 3.7.3 Accessing Configuration Space All PCI devices contain PCI configuration space, accessed using mechanism #1 defined in the PCI Local Bus Specification. If dual processors are used, only the processor designated as the boot strap processor (BSP) should perform PCI configuration space accesses. Precautions should be taken to guarantee that only one processor performs system configuration. Two Dword I/O registers in the chipset are used for the configuration space register access: CONFIG_ADDRESS (I/O address 0CF8h) CONFIG_DATA (I/O address 0CFCh) When CONFIG_ADDRESS is written to with a 32-bit value selecting the bus number, device on the bus, and specific configuration register in the device, a subsequent read or write of CONFIG_DATA initiates the data transfer to/from the selected configuration register. Byte enables are valid during accesses to CONFIG_DATA; they determine whether the configuration register is being accessed or not. Only full Dword reads and writes to CONFIG_ADDRESS are recognized as a configuration access by the chipset. All other I/O accesses to CONFIG_ADDRESS are treated as normal I/O transactions. 52 Revision 4.0