HP StorageWorks MSA 2/8 HP StorageWorks Fabric OS V3.1.x/4.1.x Reference Guide - Page 88

Fabric OS Commands Subtest 1 Subtest 2 The test consists of 6 subtests: The BISR subtest executes the Built-In-Self-Repair (BISR) circuitry in each ASIC. The BISR executes its own BIST, and cells found bad are replaced by redundant rows provided in each SRAM in the ASIC. Once replaced, the BIST is executed again. The firmware merely sets up the hardware for the BISR/BIST operation and checks the results. If the done bit in each SRAM is not set within a time-out period, it reports the DIAG-CMBISRTO. If any of the SRAMs within the ASIC fails to map out the bad rows, its fail bit is set and the DIAG-CMBISRF error generated. For V4.1.x, the firmware merely sets up the hardware for the BISR/BIST operation and checks the results. If the done bit in each SRAM is not set within a time-out period, it reports the DIAG-CMBISRTO. If any of the SRAMs within the ASIC fails to map out the bad rows, its fail bit is set and the DIAG-CMBISRF error is generated. The data write/read subtest executes the address and data bus verifications by running a specified unique ramp pattern D to all SRAMs in all ASICs in the switch. When all SRAMs are written with pattern D, the SRAMs are read and compared against the data previously written. The above step is repeated with the complemented pattern ~D to ensure that each data bit is toggled during the test. For V3.1.x, the default pattern used (by POST also) is a QUAD_RAMP with a seed value randomly obtained by reading the current content of the cpu timer counter. For example, the pattern D could take the form of: ASIC #1: 0x41176, 0x41177, 0x41178, 0x41179, ... ASIC #2: 0x51ef6, 0x51ef7, 0x51ef8, 0x51ef9, ... ASIC #3: 0x62c76, 0x62c77, 0x62c78, 0x62c79, ... ASIC #4: 0x739f6, 0x739f7, 0x739f8, 0x739f9, ... The complemented pattern ~D would then be: ASIC #1: 0xfffbee89, 0xfffbee88, 0xfffbee87, ... ASIC #2: 0xfffae109, 0xfffae108, 0xfffae107, ... 88 Fabric OS Version 3.1.x/4.1.x Reference Guide