HP Workstation x2000 hp workstation x2000 - Technical Reference and Troublesho - Page 49
Hub Interface, RDRAM Interface, RDRAM Thermal Management
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System Board Memory Controller Hub (82850) mechanism with a fully associative 20 entry TLB. Accesses between AGP and the hub interface are limited to memory writes originating from the hub interface for the AGP bus. The AGP interface is clocked from a dedicated 66 MHz clock (661N). The AGP-to-host/core interface is asynchronous. The AGP buffers operate only in 1.5V mode. They are not 3.3V safe. Hub Interface The 8-bit hub interface connects the MCH to the ICH2. Most communications between the MCH and the ICH2 occur over this interface. The hub interface runs at 66 MHz/266 MB/s. The hub interface's supported traffic types include: hub interface-to -AGP memory writes, hub interface-to-DRAM, processor-to-hub interface, messaging (MSI interrupt messages, power management state change, MI, SCI, and SERR error indication). It is assumed that the hub interface is always connected to an ICH2. RDRAM Interface The MCH directly supports two channels of Direct RDRAM memory operating in lock-step using RSL technology. These channels run at 300 MHz and 400MHz and support 128 Mb and 256 Mb technology RDRAM Direct devices. These 128 Mb and 256 Mb RDRAMs use page sizes of 1 Kb, while 256 Mb devices may also be configured to use 2 Kb pages. A maximum of 64 RDRAM devices are supported on the paired channels without external logic (128Mbit technology implies 1GB maximum in 32MB increments, whereas 256Mbit technology implies 2GB maximum in 64MB increments). The MCH also provides optional ECC error checking for RDRAM data integrity. During DRAM writes, ECC is generated on a QWord (64-bit) basis. During DRAM reads, and the read of the data that underlies partial writes, the MCH supports detection of single-bit and multiple-bit errors, and will correct single-bit errors when correction is enabled. RDRAM Thermal Management The relatively high power dissipation needs of RDRAM necessitate a MCH mechanism capable of putting a number of memory devices into a power-saving mode to keep an inadequately cooled system from Chapter 2 49