HP Workstation x2000 hp workstation x2000 - Technical Reference and Troublesho - Page 51

Figure 2-7 • RIMM B1 • RIMM B2 RIMM Memory Slots System Board Memory Controller Hub (82850) Each pair of memory sockets must contain identical memory modules (identical in size, speed, and type). That is, sockets A1 and B1 must contain identical modules, and sockets A2 and B2 must contain identical modules (or continuity modules). If you install only two RDRAM modules, use the sockets marked A1 and B1. The other two sockets (A2 and B2) must contain continuity modules. Each RIMM socket is connected to the SMBus. Read/Write Buffers The MCH defines a data-buffering scheme to support the required level of concurrent operations and provide adequate sustained bandwidth between the DRAM subsystem and all other system interfaces (CPU, AGP, and PCI). System Clocking The MCH has the following clock input pins: • Differential BCLK0/BCLK1 for the host interface • 66 MHz clock input for the AGP and hub interface • Differential CTM/CTM# and CFM/CFM# for each of the two RAC's. Clock synthesizer chip(s) are responsible for generating the system host clocks, AGP and hub interface clocks, PCI clocks and RDRAM clocks. The MCH provides two pairs of feedback signals to the Direct Rambus Clock Generator (DRCG) chips to keep the host and RDRAM clocks aligned. The host speed is 100 MHz. The RDRAM speed is 300 MHz or 400 MHz. Chapter 2 51