HP Workstation x2000 hp workstation x2000 - Technical Reference and Troublesho - Page 72

Intel Pentium IV Processor

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System Board System Bus its request (for example, for the contents of a given memory address) and release the bus, rather than waiting for the result. Therefore, processor can accept another request. The MCH, as the target device, then requests the bus again when it is ready to respond, and sends the requested data packet. As many as four transactions can be outstanding at any given time. Intel Pentium IV Processor The Pentium IV processor has several features that enhance performance: • Data bus frequency of 400MHz • Dual independent bus architecture, which combines a dedicated 64-bit Level 2 cache bus (supporting 256KB), plus a 64-bit system bus that enables multiple simultaneous transactions • MMX2 technology, which gives higher performance for media communications, and 3D applications • Dynamic execution to speed up software performance • Internet Streaming SIMD Extensions 2 (SSE2) for enhanced floating point and 3D application performance • Uses multiple low-power states, such as AutoHALT, Stop-Grant, Sleep, and Deep Sleep to conserve power during idle times The Pentium IV processor is packaged in a pin grid array (PGA) that fits into a PGA423 socket (423-pin Zero Insertion Force-ZIF-socket). Processor Clock The 100MHz system bus clock is provided by a PLL. The processor core clock is derived from the system bus by applying a ratio. This ratio is fixed in the processor. The processor then applies this ratio to the system bus clock to generate its CPU core frequency. Bus Frequencies The system board contains a 14.318MHz crystal oscillator. This frequency is multiplied to 133MHz by a phase-locked loop. An internal clock multiplier within the processor further scales this number. The bus frequency and the processor voltage are set automatically. 72 Chapter 2

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System Board
System Bus
Chapter 2
72
its request (for example, for the contents of a given memory address) and
release the bus, rather than waiting for the result. Therefore, processor
can accept another request. The MCH, as the target device, then
requests the bus again when it is ready to respond, and sends the
requested data packet. As many as four transactions can be outstanding
at any given time.
Intel Pentium IV Processor
The Pentium IV processor has several features that enhance
performance:
Data bus frequency of 400MHz
Dual independent bus architecture, which combines a dedicated
64-bit Level 2 cache bus (supporting 256KB), plus a 64-bit system bus
that enables multiple simultaneous transactions
MMX2 technology, which gives higher performance for media
communications, and 3D applications
Dynamic execution to speed up software performance
Internet Streaming SIMD Extensions 2 (SSE2) for enhanced floating
point and 3D application performance
Uses multiple low-power states, such as AutoHALT, Stop-Grant,
Sleep, and Deep Sleep to conserve power during idle times
The Pentium IV processor is packaged in a pin grid array (PGA) that fits
into a PGA423 socket (423-pin Zero Insertion Force—ZIF—socket).
Processor Clock
The 100MHz system bus clock is provided by a PLL. The processor core
clock is derived from the system bus by applying a ratio. This ratio is
fixed in the processor. The processor then applies this ratio to the system
bus clock to generate its CPU core frequency.
Bus Frequencies
The system board contains a 14.318MHz crystal oscillator. This
frequency is multiplied to 133MHz by a phase-locked loop. An internal
clock multiplier within the processor further scales this number.
The bus frequency and the processor voltage are set automatically.