AMD AMD-K6-2/400 User Guide

AMD AMD-K6-2/400 - MHz Processor Manual

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  • AMD AMD-K6-2/400 | User Guide - Page 1
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Publication # 23542 Rev: A Amendment/0 Issue Date: September 2000
  • AMD AMD-K6-2/400 | User Guide - Page 2
    or make changes to its products at any time without notice. Trademarks AMD, the AMD logo, K6, 3DNow!, and combinations thereof, AMD PowerNow!, E86, and Super7 are trademarks, FusionE86 is a service mark, and AMD-K6 and RISC86 are registered trademarks of Advanced Micro Devices, Inc. Microsoft
  • AMD AMD-K6-2/400 | User Guide - Page 3
    Information AMD-K6™-2E+ Embedded Processor Data Sheet IF YOU HAVE QUESTIONS, WE'RE HERE TO HELP YOU. The AMD customer service input concerning AMD's WWW pages can be sent via e-mail to [email protected]. Documentation and Literature Support Data books, user's manuals, data sheets, application
  • AMD AMD-K6-2/400 | User Guide - Page 4
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 To order literature: Web: www.amd.com/support/literature.html U.S. and Canada: (800) 222-9323 Third-Party Support AMD FusionE86SM program partners provide an array of products designed to meet critical time-
  • AMD AMD-K6-2/400 | User Guide - Page 5
    Data Sheet xix 1 AMD-K6™-2E+ Embedded Processor 1 1.1 AMD-K6™-2E+ Embedded Processor Features 3 1.2 Process Technology 7 1.3 Super7™ Platform 8 2 Internal Architecture 11 2.1 Microarchitecture Overview 11 2.2 Cache, Instruction Instructions Supported by the AMD-K6™-2E+ Processor Bus Frequency
  • AMD AMD-K6-2/400 | User Guide - Page 6
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 5.19 DP[7:0] (Data Parity 108 5.20 EADS# 5.57 Bus Cycle Definitions 142 6 AMD PowerNow!™ Technology 143 6.1 Enhanced Power Management Features 143 6.2 Dynamic Core Frequency and Core Voltage Control . . .
  • AMD AMD-K6-2/400 | User Guide - Page 7
    Multimedia and 3DNow!™ Execution Units 239 11.3 Floating-Point and MMX™/3DNow!™ Instruction Compatibility 240 12 System Management Mode (SMM 241 12.1 SMM Operating Mode and Default Register Values . . . . . 241 12.2 SMM State-Save Area 243 12.3 SMM Revision Identifier 245 12.4 SMM Base Address
  • AMD AMD-K6-2/400 | User Guide - Page 8
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0- MHz Bus Operation 298 16.6 Input Setup and Hold Timings for 100-MHz Bus Operation 300 16.7 Output Delay Timings for 66-MHz Bus Operation 302 16.8 Input Setup and Hold Timings for 66-MHz 333 Index 335 viii Contents
  • AMD AMD-K6-2/400 | User Guide - Page 9
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet List of Figures Figure 1. AMD-K6™-2E+ Processor Block Diagram 13 Figure 2. Cache Sector Organization 16 Figure 3. The Instruction Buffer 18 Figure 4. AMD-K6™-2E+ Processor Decode Logic 19 Figure 5. AMD-K6™-2E+ Processor Scheduler
  • AMD AMD-K6-2/400 | User Guide - Page 10
    49 Figure 39. Page Flush/Invalidate Register (PFIR 50 Figure 40. L2 Tag or Data Location for AMD-K6™-2E+ Processor-EDX 51 Figure 41. L2 Data -EAX 51 Figure 42. L2 Tag Information for AMD-K6™-2E+ Processor-EAX . . . . 52 Figure 43. Enhanced Power Management Register (EPMR 53 Figure 44. Memory
  • AMD AMD-K6-2/400 | User Guide - Page 11
    265 Figure 92. L2 Cache Sector and Line Organization 265 Figure 93. L2 Tag or Data Location for the AMD-K6™-2E+ Processor-EDX 266 Figure 94. L2 Data - EAX 267 Figure 95. L2 Tag Information for the AMD-K6™-2E+ Processor-EAX 267 Figure 96. LRU Byte 268 Figure 97. Debug Register DR7 269 Figure 98
  • AMD AMD-K6-2/400 | User Guide - Page 12
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Figure 106. Output Valid Voltage Regulator Placement 318 Figure 118. Airflow for a Heatsink with Fan 319 Figure 119. Airflow Path in a Dual-Fan System 319 Figure 120. Airflow Path in an ATX Form-Factor
  • AMD AMD-K6-2/400 | User Guide - Page 13
    Names 29 Segment Registers 30 AMD-K6™-2E+ Processor Model-Specific Registers 44 Extended Instructions 65 Floating-Point Instructions 82 MMX™ Instructions 86 3DNow!™ Instructions 89 3DNow!™ Technology DSP Extensions 90 Processor Signal State After RESET 200 Register State After RESET 201
  • AMD AMD-K6-2/400 | User Guide - Page 14
    and Invalidation 226 EWBEC Settings and Performance 231 WC/UC Memory Type 233 Valid Masks and Range Sizes AMD-K6™-2E+ Devices 290 Supported Voltages and Operating Frequencies for LowPower AMD-K6™-2E+ Processors Enabled with AMD PowerNow!™ Technology 290 CLK Switching Characteristics for 100-MHz
  • AMD AMD-K6-2/400 | User Guide - Page 15
    , Reserved, Power, and Ground Pins 325 OBGA Pin Designations by Functional Grouping 328 OBGA Pin Designations for No Connect, Reserved, Power, and Ground Pins 329 AMD-K6™-2E+ Embedded Processor Valid Ordering Part Number Combinations 334 List of Tables xv
  • AMD AMD-K6-2/400 | User Guide - Page 16
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 xvi List of Tables
  • AMD AMD-K6-2/400 | User Guide - Page 17
    September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Revision History Date September 2000 September 2000 September 2000 September 2000 Rev Description A Initial published release. A Second Printing: Revised trademarks. A Second Printing: Changed setting of NOL2 bit
  • AMD AMD-K6-2/400 | User Guide - Page 18
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 xviii Revision History
  • AMD AMD-K6-2/400 | User Guide - Page 19
    microarchitecture, implemented by the AMD-K6-2E+ processor. Chapter 3, "Software Environment" on page 27, provides a general overview of the AMD-K6-2E processor's x86 software environment and briefly describes the data types, registers, operating modes, interrupts, and instructions supported by the
  • AMD AMD-K6-2/400 | User Guide - Page 20
    Units" on page 237, describes the AMD-K6-2E+ processor's IEEE 754compatible and 854-compatible floating point execution unit, the multimedia and 3DNow!™ technology execution units, and the floating-point and MMX™/3DNow! technology instruction compatibility. Chapter 12, "System Management Mode
  • AMD AMD-K6-2/400 | User Guide - Page 21
    bottom-view connection diagrams for each package type and lists the AMD-K6-2E+ processor's pin designations by functional grouping. Chapter 19, "Package Specifications" Ordering Information" on page 333, provides the ordering part number (OPN) and valid OPN combinations. About this Data Sheet xxi
  • AMD AMD-K6-2/400 | User Guide - Page 22
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 xxii About this Data Sheet
  • AMD AMD-K6-2/400 | User Guide - Page 23
    -speed, four-way set associative, 128-Kbyte, L2 Cache x Multiport internal cache design enabling simultaneous 64-bit reads/writes of L1 and L2 caches s Super7 platform is Socket 7-compatible x Leverages high-speed 100-MHz processor bus x 2x Accelerated Graphic Port (AGP) support Chapter 1 AMD-K6
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    power with support for full 3.3 V I/O x Lower core voltages enable low-power operation s Operating frequencies x Standard-power and standard-temperature devices: 400, 450, and 500 MHz x Low-power and extended-temperature devices: 350, 400, and 450 MHz 2 AMD-K6™-2E+ Embedded Processor Chapter 1
  • AMD AMD-K6-2/400 | User Guide - Page 25
    100 MHz frontside bus, and a powerful IEEE 754-compatible and 854-compatible floating-point execution unit. The AMD-K6-2E+ processor also incorporates a superscalar MMX™ unit and AMD's innovative 3DNow! technology for high-performance multimedia and 3D graphics operation. The AMD-K6-2E+ processor is
  • AMD AMD-K6-2/400 | User Guide - Page 26
    caches simultaneously, which further enhances overall CPU throughput. The cache design is exceptionally fast, with the backside 128-Kbyte L2 cache operating at full processor speed. For example, the internal L2 cache of an AMD-K6-2E+/450 processor operates at 450 MHz and provides nine times the peak
  • AMD AMD-K6-2/400 | User Guide - Page 27
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 3DNow!™ Technology The AMD-K6-2E+ processor supports AMD's 3DNow! technology, an extension to the x86 instruction set that includes 21 new instructions to accelerate 3D graphics and other single-precision
  • AMD AMD-K6-2/400 | User Guide - Page 28
    in the AMD-K6-2E+ processor include multiple x86 instruction decode, single-clock internal RISC operations, ten execution units that support superscalar operation, out-of-order execution, data forwarding, speculative execution, and register renaming. 6 AMD-K6™-2E+ Embedded Processor Chapter 1
  • AMD AMD-K6-2/400 | User Guide - Page 29
    , high-performance 3DNow! technology and multimedia engines, x86 compatibility, and low-cost infrastructure, the AMD-K6-2E+ processor is the superior choice for high-performance embedded systems. 1.2 Process Technology The AMD-K6-2E+ processor is implemented using an AMD-developed, state
  • AMD AMD-K6-2/400 | User Guide - Page 30
    AGP graphics. 100-MHz Processor Bus The AMD-K6-2E+ processor supports a 100-MHz, 800 Mbyte/second frontside bus to provide a high-speed interface to Super7 platform-based chipsets. The 100-MHz interface speeds up access to main memory by 50 percent over the 66-MHz Socket 7 interface - resulting in
  • AMD AMD-K6-2/400 | User Guide - Page 31
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Super7™ Platform Advantages The Super7 platform: s Delivers performance and features competitive with alternate platforms at the same clock speed, and at a significantly lower cost s Takes advantage of
  • AMD AMD-K6-2/400 | User Guide - Page 32
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 10 AMD-K6™-2E+ Embedded Processor Chapter 1
  • AMD AMD-K6-2/400 | User Guide - Page 33
    the processor can run. The architecture of the AMD-K6-2E+ processor is the industry-standard x86 instruction set. s Microarchitecture refers to the design techniques used in the processor to reach the target cost, performance, and functionality goals. The AMD-K6 family of processors are based on
  • AMD AMD-K6-2/400 | User Guide - Page 34
    to include direct support for the x86 instruction set while observing the RISC performance principles of fixed length encoding, regularized instruction fields, and a large register set. The Enhanced RISC86 microarchitecture used in the AMD-K6-2E+ processor enables higher processor core performance
  • AMD AMD-K6-2/400 | User Guide - Page 35
    two x86 instructions per clock into RISC86 operations. Note: In this chapter, "clock" refers to a processor clock. The AMD-K6-2E+ processor categorizes x86 instructions into three characteristics: s Short decodes-x86 instructions less than or equal to seven bytes in length Internal Architecture 13
  • AMD AMD-K6-2/400 | User Guide - Page 36
    AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 s Long decodes-x86 instructions less than or equal to 11 bytes in length s Vector decodes-complex x86 instructions MMX or 3DNow! register operation s Simple integer, MMX or 3DNow are committed or architectural registers, consisting of
  • AMD AMD-K6-2/400 | User Guide - Page 37
    the multimedia and 3D capabilities of the x86 processor family with the introduction of 3DNow! technology, which uses a packed, single-precision, floating-point data format and Single Instruction Multiple Data (SIMD) operations based on the MMX technology model. Chapter 2 Internal Architecture 15
  • AMD AMD-K6-2/400 | User Guide - Page 38
    Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 2.2 Cache Cache, Instruction Prefetch, and Predecode Bits The writeback level-one (L1) cache on the AMD-K6-2E+ processor is organized as a separate 32-Kbyte instruction cache and a 32-Kbyte data cache with two-way set
  • AMD AMD-K6-2/400 | User Guide - Page 39
    line to be prefetched into the L1 data cache and the L2 cache. The PREFETCH instruction format is defined in Table 15, "3DNow!™ Instructions," on page 89. For more detailed information, see the 3DNow!™ Technology Manual, order# 21928. Decoding x86 instructions is particularly difficult because the
  • AMD AMD-K6-2/400 | User Guide - Page 40
    Address Stack 16 x 16 Bytes 2:1 Fetch Unit 16 Instruction Bytes plus 16 Sets of Predecode Bits Instruction Buffer Figure 3. The Instruction Buffer Instruction Decode The AMD-K6-2E+ processor decode logic is designed to decode multiple x86 instructions per clock (see Figure 4 on page 19). The
  • AMD AMD-K6-2/400 | User Guide - Page 41
    RISC86® Sequencer Vector Address 4 RISC86 Operations Figure 4. AMD-K6™-2E+ Processor Decode Logic The AMD-K6-2E+ processor uses a combination of decoders to convert x86 instructions into RISC86 operations. The hardware consists of three sets of decoders-two parallel short decoders, one long
  • AMD AMD-K6-2/400 | User Guide - Page 42
    AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 they are designed to decode up to two x86 instructions per clock. Long Decoder. The commonly-used x86 instructions that are greater than seven bytes but not more than 11 bytes long and less-commonly-used x86 instructions first set of
  • AMD AMD-K6-2/400 | User Guide - Page 43
    Information AMD-K6™-2E+ Embedded Processor Data Sheet MMX™ and 3DNow!™ Instructions. All of the MMX and 3DNow! instructions, with the exception of the EMMS, FEMMS, and PREFETCH instructions, are hardware decoded as short decodes. The MMX instruction decode generates a RISC86 MMX operation
  • AMD AMD-K6-2/400 | User Guide - Page 44
    integer, MMX, and 3DNow! execution units share the register X and Y issue pipelines. See "Register X and Y Pipelines" on page 24. The store and load execution units are two-stage pipelined designs. s The store unit performs data writes and register calculation for LEA/PUSH instructions. Data memory
  • AMD AMD-K6-2/400 | User Guide - Page 45
    has been evaluated. Table 1. Execution Latency and Throughput of Execution Units Functional Unit Store Load Integer X Multimedia (processes MMX instructions) Integer Y Branch FPU 3DNow! Function LEA/PUSH, Address (Pipelined) Memory Store (Pipelined) Memory Loads (Pipelined) Integer ALU Integer
  • AMD AMD-K6-2/400 | User Guide - Page 46
    AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Register X and Y Pipelines The functional units that execute MMX and 3DNow! instructions Y Execution Pipeline Integer X ALU MMXÉ ALU MMX/ 3DNow!É Multiplier MMX Shifter 3DNow! ALU MMX ALU Integer Y ALU Figure 6. Register
  • AMD AMD-K6-2/400 | User Guide - Page 47
    a branch execution unit. The AMD-K6-2E+ processor handles unconditional branches without any penalty by redirecting instruction fetching to the target address before the instructions are fully decoded and the processor chooses which addresses are valid. Chapter 2 Internal Architecture 25
  • AMD AMD-K6-2/400 | User Guide - Page 48
    execution unit enables efficient speculative execution. This unit gives the processor the ability to execute instructions beyond conditional branches before knowing whether the branch prediction was correct. The AMD-K6-2E+ processor does not permanently update the x86 registers or memory locations
  • AMD AMD-K6-2/400 | User Guide - Page 49
    , registers, operating modes, interrupts, and instructions supported by the AMD-K6-2E+ processor architecture and design implementation. The AMD-K6-2E+ processor implements the same ten ModelSpecific Registers (MSRs) as the AMD-K6-2 and AMD-K6-2E processors Model 8/[F:8], and the bits and fields
  • AMD AMD-K6-2/400 | User Guide - Page 50
    AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 General-Purpose Registers 31 The eight 32-bit x86 general-purpose registers are used to hold integer data or memory pointers used by instructions Used to point to data within the stack segment In order to support byte and word
  • AMD AMD-K6-2/400 | User Guide - Page 51
    /0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Integer Data Types Byte Integer Table DH DL - - - - - - - - Four types of data are used in general-purpose registers-byte, word, doubleword, and quadword integers. Figure 8 shows the format of
  • AMD AMD-K6-2/400 | User Guide - Page 52
    AMD-K6™-2E+ Embedded Processor Data Sheet instructions are located DS Data segment, where data is located ES Data segment, where data is located FS Data segment, where data is located GS Data segment, where data model, the segment register points to the base address in memory. In a protected mode
  • AMD AMD-K6-2/400 | User Guide - Page 53
    Information AMD-K6™-2E+ Embedded Processor Data Sheet Physical Memory Segment Register Real Mode Memory Model Descriptor Table Base Limit Base Base Limit Segment Base Physical Memory Segment Selector Segment Base Figure 10. Segment Usage Protected Mode Memory Model Instruction Pointer
  • AMD AMD-K6-2/400 | User Guide - Page 54
    AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 79 78 Sign The eight floating-point registers are physically 80 bits wide and labeled FPR0-FPR7. Figure 11 shows the format of the floating-point registers. See "Floating-Point Register Data 7 Stack Fault 6 Exception Flags
  • AMD AMD-K6-2/400 | User Guide - Page 55
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet The FPU control word register allows a programmer to manage the FPU processing options. Figure 13 shows the format of the FPU control word register. 15
  • AMD AMD-K6-2/400 | User Guide - Page 56
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Floating-Point Register Data Types Floating-point registers use four different types of data - packed decimal, single-precision real, double-precision real, and extended-precision real. Figures 15 and 16
  • AMD AMD-K6-2/400 | User Guide - Page 57
    floating-point register stack. The MMX and 3DNow! instructions refer to these registers as mm0 to mm7. Figure 17 shows the format of these registers. For more information, see the AMD-K6® Processor Multimedia Technology Manual, order# 20726 and the 3DNow! Technology Manual, order# 21928. 63 0 mm0
  • AMD AMD-K6-2/400 | User Guide - Page 58
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 MMX™ Technology Data Types Packed Bytes Integer 63 56 55 For the MMX instructions, the MMX registers use three types of data-packed eight-byte integer, packed quadword integer, and packed dual doubleword
  • AMD AMD-K6-2/400 | User Guide - Page 59
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 3DNow!™ Technology Data Types For 3DNow! instructions, the MMX/3DNow! registers use packed single-precision real data. Figure 19 shows the format of the 3DNow! data type. Packed Single Precision Floating
  • AMD AMD-K6-2/400 | User Guide - Page 60
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 EFLAGS Register The EFLAGS register provides for three different types of flags - system, control, and status. The system flags provide operating system
  • AMD AMD-K6-2/400 | User Guide - Page 61
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Control Registers 31 The five control registers contain system control 9 8 7 6 5 4 3 2 1 0 Page Directory Base PP CW DT Reserved Symbol Description Bit PCD Page Cache Disable 4 PWT Page Writethrough 3 Figure 22
  • AMD AMD-K6-2/400 | User Guide - Page 62
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 31 Reserved 23542A/0-September 2000 0 Figure 24. Control Register 1 (CR1) Symbol Description Bit PG Paging 31 CD Cache Disable 30 NW Not Writethrough 29 31
  • AMD AMD-K6-2/400 | User Guide - Page 63
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Debug Registers Figures 26 through 29 show the 32-bit debug registers supported by the processor. These registers are further described in "Debug" on page 268. Symbol LEN 3 R/W 3 LEN 2 R/W 2 LEN 1 R/W 1 LEN
  • AMD AMD-K6-2/400 | User Guide - Page 64
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  • AMD AMD-K6-2/400 | User Guide - Page 65
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet DR3 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Breakpoint 3 32-
  • AMD AMD-K6-2/400 | User Guide - Page 66
    EPMR register is supported in the low-power versions only of the AMD-K6-2E+ processor. For more information about the MSRs, see the Embedded AMD-K6™ Processors BIOS Design Guide Application Note, order# 23913. For more information about the RDMSR and WRMSR instructions, see the AMD K86™ Family BIOS
  • AMD AMD-K6-2/400 | User Guide - Page 67
    /0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Machine Check Address Register (MCAR) and Machine Check Type Register (MCTR) 63 The AMD-K6-2E+ processor does not support the generation of a machine check exception. However, the processor does provide a 64-bit
  • AMD AMD-K6-2/400 | User Guide - Page 68
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Test Register 12 (TR12) 63 Reserved Test the status of the Time Stamp Disable (TSD) bit in CR4. With either of these instructions, the EDX and EAX registers hold the upper and lower dwords of the 64-bit value
  • AMD AMD-K6-2/400 | User Guide - Page 69
    AMD-K6™-2E+ Embedded Processor Data Sheet Extended Feature Enable Register (EFER) 63 The Extended Feature Enable Register (EFER) contains the control bits that enable the extended features of the processor SCE must be set to 1 to enable the usage of the SYSCALL and SYSRET instructions. For more
  • AMD AMD-K6-2/400 | User Guide - Page 70
    Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 SYSCALL/SYSRET Target Address Register (STAR) The SYSCALL/SYSRET target address register (STAR) contains the target EIP address used by the SYSCALL instruction and the 16-bit code and stack segment selector bases used
  • AMD AMD-K6-2/400 | User Guide - Page 71
    Address Mask 1 C C 11 Physical Base Address 0 WU Physical Address Mask 0 C C 00 MTRR1 MTRR0 Figure 37. UC/WC Cacheability Control Register (UWCCR) Processor State Observability Register (PSOR) . 63 The AMD-K6-2E+ processor provides the Processor State Observability Register (PSOR). The PSOR
  • AMD AMD-K6-2/400 | User Guide - Page 72
    Array Access Register (L2AAR) The AMD-K6-2E+ processor provides the L2AAR register that allows for direct access to the L2 cache and L2 tag arrays. The L2AAR register is MSR C000_0089h. The operation that is performed on the L2 cache is a function of the instruction executed-RDMSR or WRMSR-and the
  • AMD AMD-K6-2/400 | User Guide - Page 73
    Octet Selects one of four octets 4-3 Dword Selects upper (1) or lower (0) dword 2 6 5 4 32 1 0 L D Set i n e Octet w o r d Figure 40. L2 Tag or Data Location for AMD-K6™-2E+ Processor-EDX If the L2 cache data is read (as opposed to reading the tag information), the result (doubleword) is
  • AMD AMD-K6-2/400 | User Guide - Page 74
    Tag Array Testing" on page 264. The AMD-K6-2E+ processor is designed with enhanced power management features, called AMD PowerNow! technology, which include dynamic bus divisor control and dynamic core voltage control. The EPMR register (see Figure 43) defines the base address for a 16-byte block of
  • AMD AMD-K6-2/400 | User Guide - Page 75
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 63 16 15 Reserved Symbol Description Bit IOBASE I/O Base Address 15-4 GSBC Generate Special Bus Cycle 1 EN Enable AMD PowerNow! Technology Management 0 Figure 43. Enhanced Power Management
  • AMD AMD-K6-2/400 | User Guide - Page 76
    Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 3.3 Memory Management Registers The AMD-K6-2E+ processor controls Function Contains a pointer to the base of the global descriptor table Contains a pointer to the base of the interrupt descriptor table Contains
  • AMD AMD-K6-2/400 | User Guide - Page 77
    AMD-K6™-2E+ Embedded Processor Data Sheet Task State Segment 31 Figure 45 shows the format of the task state segment (TSS). I/O Permission Bitmap (IOPB) (up to 8 Kbytes) 0 TSS Limit from TR Interrupt Redirection Bitmap (IRB) (eight 32-bit locations) Operating System Data Structure Base
  • AMD AMD-K6-2/400 | User Guide - Page 78
    Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 3.4 Paging The AMD-K6-2E+ processor can physically address up to four Gbytes of memory. This memory can be segmented into pages. The size of these pages is determined by the operating system design and the values set
  • AMD AMD-K6-2/400 | User Guide - Page 79
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 4-Mbyte Page Frame Page Directory PDE CR3 Physical Address 31 22 21 0 Page Directory Offset Page Offset Linear Address Figure 47. 4-Mbyte Paging Mechanism Figures
  • AMD AMD-K6-2/400 | User Guide - Page 80
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 31 Page Table Base Address Symbol Description Bits AVL Available to Software 11-9 Reserved 8 PS Page Size 7 Reserved 6 A Accessed 5 PCD Page Cache Disable 4 PWT Page Writethrough 3 U/S
  • AMD AMD-K6-2/400 | User Guide - Page 81
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 31 12 11 10 9 8 7 6 5 4 3 2 1 0 Physical Page Base Address A P P UW structures and registers in the x86 architecture that define, protect, and isolate code segments, data segments, task state segments, and
  • AMD AMD-K6-2/400 | User Guide - Page 82
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 12 11 10 9 8 7 6 5 4 3 2 1 0 Base Address 31-24 A GD V Segment P DPL 1 Type L Limit Base Address 23-16 Base Address 15-0 Segment Limit 15-0 Figure 51. Application Segment Descriptor Table 9.
  • AMD AMD-K6-2/400 | User Guide - Page 83
    /0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Reserved Symbol G X 12 11 10 9 8 7 6 5 4 3 2 1 0 Base Address 31-24 A GX V Segment P DPL 0 Type L Limit Base Address 23-16 Base Address 15-0 Segment Limit 15-0 Figure 52. System Segment Descriptor Table
  • AMD AMD-K6-2/400 | User Guide - Page 84
    AMD-K6™-2E+ Embedded Processor Data Sheet Device Not Available 8 Double Fault 9 Reserved - Interrupt fault NMI signal sampled asserted Int 3 INTO BOUND Invalid instruction ESC and WAIT Fault occurs while handling a fault - Task switch to an invalid segment Instruction instruction Data reference to an
  • AMD AMD-K6-2/400 | User Guide - Page 85
    refer to the following manuals: s MMX Instructions-AMD-K6® Processor Multimedia Technology Manual, order# 20726 s 3DNow! Technology Instructions-3DNow! Technology Manual, order# 21928 s 3DNow! Technology DSP Extensions-AMD Extensions to the 3DNow! and MMX Instruction Set Manual, order# 22466 Each
  • AMD AMD-K6-2/400 | User Guide - Page 86
    01b or 00b. The fifth column lists the type of instruction decode - short, long, and vector. The AMD-K6-2E+ processor decode logic can process two short, one long, or immediate, instruction control unit s load, fload, mload-load unit s meu-multimedia execution units for MMX and 3DNow! instructions s
  • AMD AMD-K6-2/400 | User Guide - Page 87
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Table 12. Integer Instructions Instruction Mnemonic AAA AAD AAM AAS ADC mreg8, reg8 ADC mem8, reg8 ADC mreg16/32, reg16/32 ADC mem16/32, reg16/32 ADC reg8, mreg8 ADC
  • AMD AMD-K6-2/400 | User Guide - Page 88
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Table 12. Integer Instructions (continued) Instruction Mnemonic ADD mem16/32, imm8 (signed ext.) AND mreg8, reg8 AND mem8, reg8 AND mreg16/32, reg16/32 AND mem16/32, reg16/32 AND reg8,
  • AMD AMD-K6-2/400 | User Guide - Page 89
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Table 12. Integer Instructions (continued) Instruction Mnemonic BT mem16/32, imm8 BTC mreg16/32, reg16/32 BTC mem16/32, reg16/32 BTC mreg16/32, imm8 BTC mem16/32, imm8 BTR mreg16/
  • AMD AMD-K6-2/400 | User Guide - Page 90
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Table 12. Integer Instructions (continued) Instruction Mnemonic CMP mem8, imm8 CMP mreg16/32, imm16/32 CMP mem16/32, imm16/32 CMP mreg16/32, imm8 (signed ext.) CMP mem16/32, imm8 (signed
  • AMD AMD-K6-2/400 | User Guide - Page 91
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Table 12. Integer Instructions (continued) Instruction Mnemonic First Byte IDIV mem8 F6h IDIV EAX, mreg16/32 F7h IDIV EAX, mem16/32 F7h IMUL reg16/32, imm16/32 69h IMUL reg16/32,
  • AMD AMD-K6-2/400 | User Guide - Page 92
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Table 12. Integer Instructions (continued) Instruction Mnemonic JO short disp8 JB/JNAE short disp8 JNO short disp8 JNB/JAE short disp8 JZ/JE short disp8 JNZ/JNE short disp8 JBE/JNA
  • AMD AMD-K6-2/400 | User Guide - Page 93
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Table 12. Integer Instructions (continued) Instruction Mnemonic JMP disp8 (short) JMP far mreg32 (indirect) JMP far mem32 (indirect) JMP near mreg16/32 (indirect) JMP near mem16/32 (indirect) LAHF LAR reg16/
  • AMD AMD-K6-2/400 | User Guide - Page 94
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Table 12. Integer Instructions (continued) Instruction Mnemonic MOV reg8, mreg8 MOV reg8, mem8 MOV reg16/32, mreg16/32 MOV reg16/32, mem16/32 MOV mreg16, segment reg MOV mem16, segment reg
  • AMD AMD-K6-2/400 | User Guide - Page 95
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Table 12. Integer Instructions (continued) Instruction Mnemonic MOV reg32, CR4 MOV CR0, reg32 MOV CR2, reg32 MOV CR3, reg32 MOV CR4, reg32 MOVSB mem8,mem8 MOVSD mem16, mem16 MOVSW mem32, mem32
  • AMD AMD-K6-2/400 | User Guide - Page 96
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Table 12. Integer Instructions (continued) Instruction Mnemonic OR reg16/32, mreg16/32 OR reg16/32, mem16/32 OR AL, imm8 OR EAX, imm16/32 OR mreg8, imm8 OR mem8, imm8 OR
  • AMD AMD-K6-2/400 | User Guide - Page 97
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Table 12. Integer Instructions (continued) Instruction Mnemonic PUSH FS PUSH GS PUSH SS PUSH DS PUSH EAX PUSH ECX PUSH EDX PUSH EBX PUSH ESP PUSH EBP PUSH ESI PUSH EDI
  • AMD AMD-K6-2/400 | User Guide - Page 98
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Table 12. Integer Instructions (continued) Instruction Mnemonic RCR mem8, 1 RCR mreg16/32, 1 RCR mem16/32, 1 RCR mreg8, CL RCR mem8, CL RCR mreg16/32, CL RCR mem16/32, CL RDMSR RDTSC
  • AMD AMD-K6-2/400 | User Guide - Page 99
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Table 12. Integer Instructions (continued) Instruction Mnemonic ROR mreg16/32, CL ROR mem16/32, CL RSM SAHF SAR mreg8, imm8 SAR mem8, imm8 SAR mreg16/32, imm8 SAR mem16/32, imm8
  • AMD AMD-K6-2/400 | User Guide - Page 100
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Table 12. Integer Instructions (continued) Instruction Mnemonic SETO mreg8 SETO mem8 SETNO mreg8 SETNO mem8 SETB/SETNAE mreg8 SETB/SETNAE mem8 SETNB/SETAE mreg8 SETNB/SETAE mem8 SETZ/SETE mreg8 SETZ/
  • AMD AMD-K6-2/400 | User Guide - Page 101
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Table 12. Integer Instructions (continued) Instruction Mnemonic SHL/SAL mem8, imm8 SHL/SAL mreg16/32, imm8 SHL/SAL mem16/32, imm8 SHL/SAL mreg8, 1 SHL/SAL mem8, 1 SHL/SAL mreg16/32, 1
  • AMD AMD-K6-2/400 | User Guide - Page 102
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Table 12. Integer Instructions (continued) Instruction Mnemonic STC STD STI STOSB mem8, AL STOSW mem16, AX STOSD mem32, EAX STR mreg16 STR mem16 SUB mreg8, reg8 SUB mem8, reg8 SUB mreg16/
  • AMD AMD-K6-2/400 | User Guide - Page 103
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Table 12. Integer Instructions (continued) Instruction Mnemonic TEST mem16/32, imm16/32 VERR mreg16 VERR mem16 VERW mreg16 VERW mem16 WAIT WBINVD WRMSR XADD mreg8, reg8 XADD mem8, reg8 XADD mreg16/
  • AMD AMD-K6-2/400 | User Guide - Page 104
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Table 12. Integer Instructions (continued) Instruction Mnemonic XOR mreg8, imm8 XOR mem8, imm8 XOR mreg16/32, imm16/32 XOR mem16/32, imm16/32 XOR mreg16/32, imm8 (signed ext.) XOR mem16/
  • AMD AMD-K6-2/400 | User Guide - Page 105
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Table 13. Floating-Point Instructions (continued) Instruction Mnemonic FDIV ST(i), ST(0) (single precision)1 FDIV ST(i), ST(0) (double precision)1 FDIV ST(i), ST(0) (extended precision)1 FDIV ST(0),
  • AMD AMD-K6-2/400 | User Guide - Page 106
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Table 13. Floating-Point Instructions (continued) Instruction Mnemonic FISUB ST(0), mem32int FISUB ST(0), mem16int FISUBR ST(0), mem32int FISUBR ST(0), mem16int FLD ST(i)1 FLD mem32real FLD mem64real FLD
  • AMD AMD-K6-2/400 | User Guide - Page 107
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Table 13. Floating-Point Instructions (continued) Instruction Mnemonic FSQRT (extended precision) FST mem32real FST mem64real FST ST(i)1 FSTCW FSTENV FSTP mem32real FSTP mem64real FSTP mem80real FSTP ST(i)1
  • AMD AMD-K6-2/400 | User Guide - Page 108
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Table 14. MMX™ Instructions Instruction Mnemonic EMMS MOVD mmreg, mreg321 MOVD mmreg, mem32 MOVD mreg32, mmreg1 MOVD mem32, mmreg MOVQ mmreg1, mmreg2 MOVQ mmreg, mem64 MOVQ mmreg2, mmreg1 MOVQ mem64,
  • AMD AMD-K6-2/400 | User Guide - Page 109
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Table 14. MMX™ Instructions (continued) Instruction Mnemonic PCMPEQB mmreg, mem64 PCMPEQD mmreg1, mmreg2 PCMPEQD mmreg, mem64 PCMPEQW mmreg1, mmreg2 PCMPEQW mmreg, mem64 PCMPGTB mmreg1, mmreg2 PCMPGTB mmreg,
  • AMD AMD-K6-2/400 | User Guide - Page 110
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Table 14. MMX™ Instructions (continued) Instruction Mnemonic PSRLD mmreg, mem64 PSRLD mmreg, imm8 PSRLQ mmreg1, mmreg2 PSRLQ mmreg, mem64 PSRLQ mmreg, imm8 PSRLW mmreg1, mmreg2 PSRLW mmreg, mem64 PSRLW mmreg
  • AMD AMD-K6-2/400 | User Guide - Page 111
    Data Sheet Table 14. MMX™ Instructions (continued) Instruction Mnemonic PXOR mmreg, mem64 Prefix First Byte(s) Byte 0Fh EFh Notes: 1. Bits 2, 1, and 0 of the modR/M byte select the integer register. ModR/M Byte mm-xxx-xxx Decode Type short RISC86 Operations mload, meu Table 15. 3DNow
  • AMD AMD-K6-2/400 | User Guide - Page 112
    be prefetched. 2. PREFETCHW will be implemented in a future K86 processor. On the AMD-K6-2E+ processor, this instruction performs in the same man- ner as the PREFETCH instruction. Table 16. 3DNow!™ Technology DSP Extensions Instruction Mnemonic PF2IW mmreg1, mmreg2 PF2IW mmreg, mem64 PFNACC mmreg1
  • AMD AMD-K6-2/400 | User Guide - Page 113
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 4 Logic Symbol Diagram Clock Voltage of the processor. Signals with doubleheaded arrows are bidirectional. Signals with pound signs (#) are active Low. 2. The VID[4:0] outputs are supported on low
  • AMD AMD-K6-2/400 | User Guide - Page 114
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 92 Logic Symbol Diagram Chapter 4
  • AMD AMD-K6-2/400 | User Guide - Page 115
    AMD-K6™-2E+ Embedded Processor Data Sheet 5 Signal Descriptions This chapter includes a detailed description of each signal supported on the AMD-K6-2E+ processor Sampled-The processor has measured the state of a signal at predefined points in time and will take the appropriate action based on the
  • AMD AMD-K6-2/400 | User Guide - Page 116
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 5.2 A20M# (Address Bit 20 Mask) Pin Attribute Input Summary A20M# is used to simulate the behavior of the 8086 when running in Real mode. The assertion of A20M # causes the processor to force bit 20 of
  • AMD AMD-K6-2/400 | User Guide - Page 117
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 5.3 A[31:3] (Address Bus) Pin Attribute Summary A[31:5] Bidirectional, A[4:3] Output A[31:3] contain the physical address for the current bus cycle. The processor drives addresses on A[31:3] during memory
  • AMD AMD-K6-2/400 | User Guide - Page 118
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 5.4 ADS# (Address Strobe) is sampled asserted, resulting in a single idle state between cycles. For pipelined cycles if the processor is prepared to start a new cycle, ADS # can be asserted as early as one
  • AMD AMD-K6-2/400 | User Guide - Page 119
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 5.6 AHOLD (Address Hold) Pin Attribute Summary Input AHOLD can be asserted by the system to initiate one or more inquire cycles. To allow the system
  • AMD AMD-K6-2/400 | User Guide - Page 120
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 5.7 AP (Address Parity to the assertion of this signal. Driven, Sampled, and Floated As an Output: The processor drives AP valid off the clock edge on which ADS# is asserted until the clock edge
  • AMD AMD-K6-2/400 | User Guide - Page 121
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 5.8 APCHK# (Address Parity Check) Pin Attribute Summary Output If the processor detects an address parity error during an inquire cycle, APCHK# is asserted for one clock. The processor does not take an
  • AMD AMD-K6-2/400 | User Guide - Page 122
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 5.9 BE[7:0]# (Byte Enables) Pin Attribute Output Summary BE[7:0]# are used by the processor to indicate the valid data bytes during a write cycle and the requested data bytes during a read cycle. The
  • AMD AMD-K6-2/400 | User Guide - Page 123
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 5.10 BF[2:0] (Bus Frequency) Pin Attribute Summary Inputs, Internal Pullups BF[2:0] determine the internal operating frequency of the processor. The frequency of the CLK input signal is multiplied
  • AMD AMD-K6-2/400 | User Guide - Page 124
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 5.11 BOFF# (Backoff) Pin Attribute Summary Input If BOFF # is sampled asserted, the processor unconditionally aborts any cycles in progress and transitions to a bus hold state by floating the following
  • AMD AMD-K6-2/400 | User Guide - Page 125
    Information AMD-K6™-2E+ Embedded Processor Data Sheet 5.12 BRDY# (Burst Ready) Pin Attribute Input, Internal Pullup Summary Sampled BRDY# is asserted to the processor by system logic to indicate either that the data bus is being driven with valid data during a read cycle or that the data bus
  • AMD AMD-K6-2/400 | User Guide - Page 126
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 5.13 BRDYC# (Burst Ready ADS#. 5.14 BREQ (Bus Request) Pin Attribute Summary Output BREQ is asserted by the processor to request the bus in order to complete an internally pending bus cycle. The system
  • AMD AMD-K6-2/400 | User Guide - Page 127
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 5.15 CACHE# (Cacheable Access) Pin Attribute Summary Output For reads, CACHE# is asserted to indicate the cacheability of the current bus cycle. In addition, if the processor samples KEN # asserted, which
  • AMD AMD-K6-2/400 | User Guide - Page 128
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 5.17 D/C# (Data/Code) Pin Attribute Summary Output The processor drives D/C # during a memory bus cycle to indicate whether it is addressing data or executable code. D/C# is also used to define other bus
  • AMD AMD-K6-2/400 | User Guide - Page 129
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 5.18 D[63:0] (Data Bus) Pin Attribute Summary Driven, Sampled, and Floated Bidirectional D[63:0] represent the processor's 64-bit data bus. Each of the eight bytes of data that comprise this bus is
  • AMD AMD-K6-2/400 | User Guide - Page 130
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 5.19 DP[7:0] (Data Parity) Pin Attribute Bidirectional Summary DP[7:0] are even parity bits for each valid byte of data - as defined by BE[7:0]#-driven and sampled on the D[63:0] data bus. Even parity
  • AMD AMD-K6-2/400 | User Guide - Page 131
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet The processor always floats DP[7:0] except when they are being driven during a write cycle as described above. In addition, DP[7:0] are floated off the clock edge that
  • AMD AMD-K6-2/400 | User Guide - Page 132
    Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 5.21 EWBE# (External Write Buffer Empty) Pin Attribute Input Summary The system logic can negate EWBE# to the processor to indicate that its external write buffers are full and that additional data cannot
  • AMD AMD-K6-2/400 | User Guide - Page 133
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 5.22 FERR# (Floating-Point Error) Pin Attribute Output Summary The assertion of FERR # indicates the occurrence of an unmasked floating-point exception resulting from the execution of a floating-point instruction. This signal
  • AMD AMD-K6-2/400 | User Guide - Page 134
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 5.23 FLUSH# (Cache Flush) Pin Attribute Input Summary In response to sampling FLUSH# asserted, the processor writes back any cache lines in the L1 data cache or L2 cache that are in the modified state,
  • AMD AMD-K6-2/400 | User Guide - Page 135
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 5.24 HIT# (Inquire Cycle Hit) Pin Attribute Summary Driven Output The processor asserts HIT# during an inquire cycle to indicate that the cache line is valid within the processor's L1 and/or L2 caches (
  • AMD AMD-K6-2/400 | User Guide - Page 136
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 5.26 HLDA (Hold Acknowledge) Pin Attribute Summary Output When HOLD is sampled asserted, the processor completes the current bus cycles, floats the processor bus, and asserts HLDA in an acknowledgment that
  • AMD AMD-K6-2/400 | User Guide - Page 137
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 5.27 HOLD (Bus Hold Request) Pin Attribute Summary Input The system logic can assert HOLD to gain control of the processor's bus. When HOLD is sampled asserted, the processor completes the current bus
  • AMD AMD-K6-2/400 | User Guide - Page 138
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 5. , MMX i n st r u c t i on , 3D N ow ! instruction, or the WAIT instruction-hereafter referred to as the target instruction. If an unmasked floating-point exception is pending and the target instruction is
  • AMD AMD-K6-2/400 | User Guide - Page 139
    AMD-K6™-2E+ Embedded Processor Data Sheet Sampled This signal is provided to allow the system logic to handle exceptions in a manner consistent with IBM-compatible PC/AT systems. The processor clock edge but is not recognized until the next instruction boundary. During an I/O write cycle, it must
  • AMD AMD-K6-2/400 | User Guide - Page 140
    Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 5.30 INTR (Maskable Interrupt) Pin Attribute Summary Sampled Input INTR is the system's maskable interrupt input to the processor. When the processor samples and recognizes INTR asserted, the processor executes
  • AMD AMD-K6-2/400 | User Guide - Page 141
    2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 5.32 KEN# (Cache Enable) Pin Attribute Summary Input If KEN # is sampled asserted, it indicates that the address presented by the processor is cacheable. If KEN # is sampled asserted and the processor intends to perform
  • AMD AMD-K6-2/400 | User Guide - Page 142
    Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 5.33 LOCK# (Bus Lock) Pin Attribute Output Summary The processor accesses s Page Directory and Page Table accesses s XCHG instruction s An instruction with an allowable LOCK prefix In order to ensure that locked
  • AMD AMD-K6-2/400 | User Guide - Page 143
    Processor Data Sheet 5.34 M/IO# (Memory or I/O) Pin Attribute Summary Output The processor drives M/IO# during a bus cycle to indicate whether it is addressing the memory or I/O space. If M/IO# = 1, the processor is addressing memory or a memory-mapped I/O port as the result of an instruction
  • AMD AMD-K6-2/400 | User Guide - Page 144
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 5.35 NA# (Next Address) Pin Attribute Summary Input System logic asserts NA# to indicate to the processor that it is ready to accept another bus cycle pipelined into the previous bus cycle. ADS#, along
  • AMD AMD-K6-2/400 | User Guide - Page 145
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 5.36 NMI (Non-Maskable Interrupt) Pin Attribute Input Summary When NMI is sampled asserted, the processor jumps to the interrupt service routine defined by interrupt number 02h. Unlike the INTR signal,
  • AMD AMD-K6-2/400 | User Guide - Page 146
    AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 5.37 PCD (Page Cache Disable) Pin Attribute Output Summary The processor -8086 modes while caching is enabled (CD bit in CR0 set to 0) and paging is enabled (PG bit in CR0 set to 1): • For accesses to I/O space, page directory
  • AMD AMD-K6-2/400 | User Guide - Page 147
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 5.38 PCHK# (Parity Check) Pin Attribute Summary Output The processor asserts PCHK# during read cycles if it detects an even parity error on one or more valid bytes of D[63:0] during a read cycle. (Even
  • AMD AMD-K6-2/400 | User Guide - Page 148
    AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 5.39 PWT (Page Writethrough) Pin Attribute Output Summary The processor s In Protected and Virtual-8086 modes while paging is enabled (PG bit in CR0 set to 1): • For accesses to I/O space, page directory entries, and other non-
  • AMD AMD-K6-2/400 | User Guide - Page 149
    Processor Data Sheet 5.40 RESET (Reset) Pin Attribute Summary Input When the processor samples RESET asserted, it immediately flushes and initializes all internal resources and its internal state including its pipelines and caches, the floating-point state, the MMX state, the 3DNow! state
  • AMD AMD-K6-2/400 | User Guide - Page 150
    to the system logic as defined by the industry-standard Super7 and Socket 7 interface s Any combination of NC and Socket 7 pins In any case, if the RSVD pins are treated accordingly, the normal operation of the AMD-K6-2E+ processor is not adversely affected in any manner. 128 Signal Descriptions
  • AMD AMD-K6-2/400 | User Guide - Page 151
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 5.42 SCYC (Split Cycle) Pin Attribute Output Summary The processor asserts SCYC during misaligned, locked transfers on the D[63:0] data bus. The processor generates additional bus cycles to complete the
  • AMD AMD-K6-2/400 | User Guide - Page 152
    is not affected by EWBE#) 4. Saves the internal processor state in SMM memory 5. Disables interrupts by clearing the interrupt flag (IF) in EFLAGS and disables NMI interrupts 6. Jumps to the entry point of the SMM service routine at the SMM base physical address, which defaults to 0003_8000h in SMM
  • AMD AMD-K6-2/400 | User Guide - Page 153
    /0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 5.44 SMIACT# (System Management Interrupt Active) Pin Attribute Summary Output The processor acknowledges the assertion of SMI# with the assertion of SMIACT# to indicate that the processor has entered System
  • AMD AMD-K6-2/400 | User Guide - Page 154
    AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 5.45 STPCLK# (Stop Clock) Pin Attribute Summary Input, Internal Pullup The assertion of STPCLK# causes the processor to enter the Stop Grant state, during which the processor until the next instruction boundary. System logic
  • AMD AMD-K6-2/400 | User Guide - Page 155
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 5.46 TCK (Test Clock) Pin processor always samples TCK, except while TRST# is asserted. 5.47 TDI (Test Data Input) Pin Attribute Summary Input, Internal Pullup TDI is the serial test data and instruction
  • AMD AMD-K6-2/400 | User Guide - Page 156
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 5.49 TMS (Test Mode Access Port (TAP)" on page 253 for details regarding the operation of the TAP controller. The processor samples TMS on every rising TCK edge. If TMS is sampled High for five or more
  • AMD AMD-K6-2/400 | User Guide - Page 157
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 5.51 VCC2DET (VCC2 Detect) Pin Attribute Summary Output (supported on the CPGA package only) VCC2DET is internally tied to VSS (logic level 0) to indicate to the system logic that it must supply the
  • AMD AMD-K6-2/400 | User Guide - Page 158
    s VCC2H/L# is driven Low for all AMD-K6 processors with a core voltage requirement of 2.4 V or less. Note that all AMD products based on the 0.18-micron process technology, including the AMD-K6-2E+ processor, are 2.0 V or less. Driven Note that this pin is not supported on the OBGA package. VCC2H
  • AMD AMD-K6-2/400 | User Guide - Page 159
    when RESET is sampled asserted. Note that these pins are supported on the low-power versions only of the AMD-K6-2+ processor. For more information about these signals, see the Embedded AMD-K6™ Processors BIOS Design Guide Application Note, order# 23913. Driven VID[4:0] are initialized to the
  • AMD AMD-K6-2/400 | User Guide - Page 160
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 5.54 W/R# (Write/Read) Pin Attribute Summary Output The processor drives W/R# to indicate whether it is performing a write or a read cycle on the bus. In addition, W/R# is used to define other bus cycles,
  • AMD AMD-K6-2/400 | User Guide - Page 161
    AMD-K6™-2E+ Embedded Processor Data Sheet 5.55 WB/WT# (Writeback or Writethrough) Pin Attribute Input Summary WB/WT#, together with PWT, specifies the data inquire cycle, an internal snoop, a flush operation, or the WBINVD instruction. Sampled WB/WT# is sampled on the clock edge that the
  • AMD AMD-K6-2/400 | User Guide - Page 162
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 5.56 Pin Tables by Type Table clocks prior to its negation. 6. When register bit EFER[3] is set to 1, EWBE# is ignored by the processor. 7. FLUSH# is also sampled during the falling transition of RESET and
  • AMD AMD-K6-2/400 | User Guide - Page 163
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Table 20. Output Pin Float Conditions Name A[4:3]2,3 asserted. 3. Floated off the clock edge that AHOLD is sampled asserted. 4. Supported on the low-power versions only. Table 21. Input/Output Pin Float
  • AMD AMD-K6-2/400 | User Guide - Page 164
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 5.57 Bus Cycle Definitions Table 23. Bus Cycle Definition Bus Cycle Initiated Code Read, L1 Instruction Cache and L2 Cache Line Fill Code Read, Noncacheable Code Read, Noncacheable Encoding for Special
  • AMD AMD-K6-2/400 | User Guide - Page 165
    power versions of the AMD-K6-2E+ processor to support AMD PowerNow! technology features. The EPMR and PSOR registers and the I/O block are defined in this section, followed by a discussion of how to implement and use the AMD PowerNow! technology features (see "Dynamic Core Frequency and Core Voltage
  • AMD AMD-K6-2/400 | User Guide - Page 166
    , see the Embedded AMD-K6™ Processors BIOS Design Guide Application Note, order# 23913. 63 16 15 4 3 21 0 G IOBASE SE BN C Reserved Symbol Description Bit IOBASE I/O Base Address 15-4 GSBC Generate Special Bus Cycle 1 EN Enable AMD PowerNow! Technology Management 0 Figure 54
  • AMD AMD-K6-2/400 | User Guide - Page 167
    AMD-K6™-2E+ Embedded Processor Data Sheet Table 25. Enhanced Power Management Register (EPMR) Definition Bit Description 63-16 Reserved 15-4 I/O BASE Address (IOBASE) 3-2 Reserved 1 Generate Special Bus Cycle (GSBC) 0 Enable AMD PowerNow! Technology GSBC bit is enabled (set to 1), a special bus
  • AMD AMD-K6-2/400 | User Guide - Page 168
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 EPM 16-Byte I/O Block 15 The EPM 16-byte I/O block contains one 4-byte field-Bus the function of each bit of the BVC field located within the EPM 16-byte I/O block. 146 AMD PowerNow!™ Technology Chapter 6
  • AMD AMD-K6-2/400 | User Guide - Page 169
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 31 12 11 10 9 8 7 54 0 BV processor VID[4:0] pins at RESET. Notes: 1. All bits default to 0 when RESET is asserted, except the VIDO bits which default to 01010b. Chapter 6 AMD PowerNow!™ Technology
  • AMD AMD-K6-2/400 | User Guide - Page 170
    the processor support the PSOR register as defined on page 49. The PSOR register is MSR C000_0087h. . Symbol PBF VID Description Pin Bus Frequency Divisor Note: Low-power AMD-K6-2E+ processors support AMD PowerNow! technology, which enables dynamic alteration of the processor's core voltage.
  • AMD AMD-K6-2/400 | User Guide - Page 171
    frequency of the processor bus. Table 28. Processor-to-Bus Clock Ratios State of EBF[2:0] 100b 101b 110b 111b 000b 001b 010b 011b Processor-to-Bus Clock Ratio 2.0x1 3.0x 6.0x 3.5x 4.5x 5.0x 4.0x 5.5x Notes: 1. The AMD-K6-2E+ processor does not support the 2.5x ratio supported by earlier AMD-K6
  • AMD AMD-K6-2/400 | User Guide - Page 172
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 6.2 Dynamic Core Frequency and Core Voltage Control AMD PowerNow! technology-enabled processors support the ability to change the bus frequency divisor and core voltage transparently to the user during run-
  • AMD AMD-K6-2/400 | User Guide - Page 173
    and transitions the CPU core voltage and frequency to the values specified in the VIDO and IBF fields of the BVC field. Note: System-initiated inquire (snoop) cycles are not supported and must be prevented during the EPM Stop Grant state. AMD PowerNow! technology-enabled processors feature Voltage
  • AMD AMD-K6-2/400 | User Guide - Page 174
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 152 AMD PowerNow!™ Technology Chapter 6
  • AMD AMD-K6-2/400 | User Guide - Page 175
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 7 Bus Cycles The following sections describe and illustrate the timing and relationship of bus signals during various types of bus cycles. A representative set of bus cycles is illustrated. 7.1 Timing
  • AMD AMD-K6-2/400 | User Guide - Page 176
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Active High Signals Active Low Signals For all active High signals, the term asserted means the signal is in the High-voltage
  • AMD AMD-K6-2/400 | User Guide - Page 177
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 7.2 Bus States The bus states illustrated in Figure 59 are described in this section. Addr No Pending Yes Request? Address Bus State Branch Condition Idle Idle Data Data Yes Last BRDY# No
  • AMD AMD-K6-2/400 | User Guide - Page 178
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Idle Address Data Data-NA# Requested Pipeline Address The processor does not drive the system bus in the Idle state and remains in this state until a new bus cycle is requested. The processor enters this
  • AMD AMD-K6-2/400 | User Guide - Page 179
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Pipeline Data Transition sampled asserted). If the last BRDY# is not sampled asserted, the processor enters the Pipeline Data state. If the processor samples the last BRDY# asserted in this state, it
  • AMD AMD-K6-2/400 | User Guide - Page 180
    AMD-K6-2E+ processor performs single or burst-memory bus cycles. s The single-transfer memory bus cycle transfers 1, 2, 4, or 8 bytes and requires a minimum of two clocks. s Misaligned instructions during the BRDY# to indicate its support for cacheability. The processor (which drives CACHE#) and the
  • AMD AMD-K6-2/400 | User Guide - Page 181
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Figure 60, the second write cycle occurs during the execution of a serializing instruction. The processor delays the following cycle until EWBE# is sampled asserted. CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R#
  • AMD AMD-K6-2/400 | User Guide - Page 182
    , it determines the appropriate pair of bus cycles - each with its own ADS# and BRDY# - required to complete the access. The AMD-K6-2E+ processor performs misaligned memory reads and memory writes using least-significant bytes (LSBs) first followed by most-significant bytes (MSBs). Table 29 shows
  • AMD AMD-K6-2/400 | User Guide - Page 183
    /0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# D[63:0] BRDY# Memory Read (Misaligned) Memory Write (Misaligned) ADDR DATA DATA IDLE ADDR DATA DATA IDLE ADDR DATA DATA DATA IDLE ADDR DATA DATA DATA IDLE LSB MSB LSB
  • AMD AMD-K6-2/400 | User Guide - Page 184
    62 on page 163 shows normal burst read cycles and a pipelined burst read cycle. The AMD-K6-2E+ processor drives CACHE# and ADS# together to specify that the current bus cycle is a burst cycle. If the processor samples KEN# asserted with the first BRDY#, it performs burst transfers. During the burst
  • AMD AMD-K6-2/400 | User Guide - Page 185
    2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# NA# D[63:0] CACHE# KEN# BRDY# Burst Read Burst Read Pipelined Burst Read ADDR DATA DATA DATA DATA IDLE ADDR DATA DATA DATA -NA PIPE -ADDR DATA DATA DATA DATA IDLE ADDR1
  • AMD AMD-K6-2/400 | User Guide - Page 186
    The AMD-K6-2E+ processor initiates writebacks under the following conditions: s Replacement-If a cache-line fill is initiated for a cache line currently filled with valid entries, the processor selects a line for replacement based on a least-recently-used (LRU) algorithm for the L1 instruction cache
  • AMD AMD-K6-2/400 | User Guide - Page 187
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet CLK A[31:3] BE[7:0]# ADS# CACHE# M/IO# D/C# W/R# D[63:0] KEN# BRDY# WB/WT# Burst Read Burst Writeback from L1 Cache ADDR DATA DATA DATA DATA IDLE ADDR DATA DATA DATA DATA IDLE Figure 63. Burst Writeback
  • AMD AMD-K6-2/400 | User Guide - Page 188
    Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 7.4 I/O Read and Write Basic I/O Read and Write The processor accesses I/O when it executes an I/O instruction (for example, IN or OUT). Figure 64 shows an I/O read followed by an I/O write. The processor drives
  • AMD AMD-K6-2/400 | User Guide - Page 189
    Write Table 31 shows the misaligned I/O read and write cycle order executed by the AMD-K6-2E+ processor. In Figure 65, the least-significant bytes (LSBs) are transferred first. Immediately after the processor samples BRDY# asserted, it drives the second bus cycle to transfer the most-significant
  • AMD AMD-K6-2/400 | User Guide - Page 190
    AMD-K6-2E+ processor provides built-in level-one (L1) data and instruction caches, and a unified level-two (L2) cache. Each L1 cache is 32 Kbytes and two-way set inquire cycles, the processor floats all of its bus-driving signals. The AMD-K6-2E+ processor does not support system-initiated inquire
  • AMD AMD-K6-2/400 | User Guide - Page 191
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# D[63:0] HOLD HLDA BRDY# Figure 66 on page 169 shows a basic HOLD/HLDA operation. In this example, the processor samples HOLD asserted during the memory read cycle.
  • AMD AMD-K6-2/400 | User Guide - Page 192
    Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 HOLD-Initiated Inquire Hit to Shared or Exclusive Line Figure 67 on page 171 shows a HOLD-initiated inquire cycle. In this example, the processor samples HOLD asserted during the burst memory read cycle. The processor
  • AMD AMD-K6-2/400 | User Guide - Page 193
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# HIT# HITM# D[63:0] KEN# BRDY# HOLD HLDA EADS# INV Burst Memory Read Figure 67. HOLD-Initiated Inquire Hit to Shared
  • AMD AMD-K6-2/400 | User Guide - Page 194
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 HOLD-Initiated Inquire Hit to Modified Line Figure 68 on page 173 shows the same sequence as Figure 67 on page 171, but in Figure 68 the inquire cycle hits a modified line and the processor asserts both HIT#
  • AMD AMD-K6-2/400 | User Guide - Page 195
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# HIT# HITM# D[63:0] KEN# BRDY# HOLD HLDA EADS# INV Burst Memory Read Inquire Figure 68. HOLD-Initiated Inquire Hit to
  • AMD AMD-K6-2/400 | User Guide - Page 196
    . The system logic drives EADS# with an inquire address on A[31:5] during an inquire cycle. The processor samples EADS# asserted and compares the inquire address to its tag address in the L1 instruction and data caches, and in the L2 cache. In Figure 69, the inquire address misses the tag address in
  • AMD AMD-K6-2/400 | User Guide - Page 197
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Read CLK A[31:3] BE[7:0]# AP APCHK# ADS# HIT# HITM# D[63:0] KEN# BRDY# AHOLD EADS# INV Figure 69. AHOLD-Initiated Inquire Miss Inquire Chapter 7 Bus Cycles 175
  • AMD AMD-K6-2/400 | User Guide - Page 198
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 AHOLD-Initiated Inquire Hit to Shared or Exclusive Line In Figure 70 on page 177, the processor asserts HIT# and negates HITM# off the clock edge after the clock edge on which EADS# is sampled asserted,
  • AMD AMD-K6-2/400 | User Guide - Page 199
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# HIT# HITM# D[63:0] KEN# BRDY# AHOLD EADS# INV Burst Memory Read Inquire Figure 70. AHOLD-Initiated Inquire Hit to Shared
  • AMD AMD-K6-2/400 | User Guide - Page 200
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 AHOLD-Initiated Inquire Hit to Modified Line Figure 71 on page 179 shows an AHOLD-initiated inquire cycle that hits a modified line. During the inquire cycle in this example, the processor asserts both HIT#
  • AMD AMD-K6-2/400 | User Guide - Page 201
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# HIT# HITM# D[63:0] KEN# BRDY# AHOLD EADS# INV Burst Memory Read Inquire Figure 71. AHOLD-Initiated Inquire Hit to Modified
  • AMD AMD-K6-2/400 | User Guide - Page 202
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 AHOLD Restriction When the system logic drives an AHOLD-initiated inquire cycle, it must assert AHOLD for at least two clocks before it asserts EADS#. This requirement guarantees the processor recognizes and
  • AMD AMD-K6-2/400 | User Guide - Page 203
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet CLK ADS# W/R# HITM# EADS# D[63:0] BRDY# Legal AHOLD negation during write cycle AHOLD Illegal AHOLD negation during write cycle The system must ensure that AHOLD
  • AMD AMD-K6-2/400 | User Guide - Page 204
    Processor Data Sheet 23542A/0-September 2000 Bus Backoff (BOFF#) BOFF# provides the fastest response among bus-hold inputs. Either the system logic or another bus master can assert BOFF# to gain control of the bus immediately. BOFF# is also used to resolve potential deadlock problems that
  • AMD AMD-K6-2/400 | User Guide - Page 205
    23542A/0-September 2000 Read CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# BOFF# D[63:0] BRDY# Figure 73. BOFF# Timing Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Backoff Cycle Restart Read Cycle Chapter 7 Bus Cycles 183
  • AMD AMD-K6-2/400 | User Guide - Page 206
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Locked Cycles Basic Locked Operation The processor asserts LOCK# during a sequence of bus cycles to ensure the cycles are completed without allowing other bus masters to intervene. Locked operations can
  • AMD AMD-K6-2/400 | User Guide - Page 207
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet CLK A[31:3] BE[7:0]# ADS# LOCK# M/IO# D/C# W/R# SCYC D[63:0] BRDY# Locked Read Cycle Locked Write Cycle ADDR DATA DATA DATA IDLE IDLE ADDR DATA DATA DATA IDLE IDLE ADDR Figure 74. Basic Locked Operation
  • AMD AMD-K6-2/400 | User Guide - Page 208
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Locked Operation with BOFF# Intervention Figure 75 on page 187 shows BOFF# asserted within a locked read-write pair of bus cycles. In this example, the processor asserts LOCK# with ADS# to drive a locked
  • AMD AMD-K6-2/400 | User Guide - Page 209
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet CLK A[31:3] BE[7:0]# ADS# LOCK# M/IO# D/C# W/R# BOFF# D[63:0] BRDY# Locked Read Cycle Aborted Write Cycle Figure 75. Locked Operation with BOFF# Intervention Restart Write Cycle
  • AMD AMD-K6-2/400 | User Guide - Page 210
    AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Interrupt Acknowledge In response to recognizing the system's maskable interrupt (INTR), the processor drives an interrupt acknowledge cycle at the next instru cti on boundary. Dur ing an inter rupt acknowledge cycle, the processor
  • AMD AMD-K6-2/400 | User Guide - Page 211
    23542A/0-September 2000 CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# LOCK# INTR D[63:0] KEN# BRDY# Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Interrupt Acknowledge Cycles Interrupt Number Figure 76. Interrupt Acknowledge Operation Chapter 7 Bus Cycles 189
  • AMD AMD-K6-2/400 | User Guide - Page 212
    and the GSBC bit of the EPMR register is set to 1 FLUSH# sampled asserted WBINVD instruction HLT instruction INVD,WBINVD instruction Triple fault Basic Special Bus Cycle Figure 77 on page 191 shows a basic special bus cycle. The processor drives D/C# = 0, M/IO# = 0, and W/R# = 1 off the same clock
  • AMD AMD-K6-2/400 | User Guide - Page 213
    2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# BRDY# Table 33). A halt special cycle is generated after the processor executes the HLT instruction. If the processor samples FLUSH# asserted, it writes back any L1 data cache and L2
  • AMD AMD-K6-2/400 | User Guide - Page 214
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Shutdown Cycle CLK A[31:3] BE[7:0]# ADS# LOCK# M/IO# D/C# W/R# D[63:0] KEN# BRDY# In Figure 78 on page 192, a shutdown (triple fault) occurs in the first half of the waveform, and a shutdown special cycle
  • AMD AMD-K6-2/400 | User Guide - Page 215
    AMD-K6™-2E+ Embedded Processor Data Sheet Stop Grant and Stop Clock States Figure 79 on page 194 and Figure 80 on page 195 show the processor on every clock edge but is not recognized until the next instruction boundary. The system logic drives the signal either synchronously or asynchronously
  • AMD AMD-K6-2/400 | User Guide - Page 216
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# CACHE# STPCLK# D[63:0] KEN# BRDY# STPCLK# Sampled Asserted Stop Grant Special Cycle Stop Clock A[4:3] = 10b FBh Figure
  • AMD AMD-K6-2/400 | User Guide - Page 217
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Stop Clock CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# CACHE# STPCLK# D[63:0] KEN# BRDY# Stop Grant State STPCLK# Sampled Negated Normal (Re-entered after PLL stabilization) Figure
  • AMD AMD-K6-2/400 | User Guide - Page 218
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 INIT-Initiated Transition from Protected Mode to Real Mode INIT is typically asserted in response to a BIOS interrupt that writes to an I/O
  • AMD AMD-K6-2/400 | User Guide - Page 219
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# D[63:0] KEN# BRDY# INIT INIT Sampled Asserted Code Fetch FFFF_FFF0h Figure 81. INIT-Initiated Transition from Protected Mode to Real
  • AMD AMD-K6-2/400 | User Guide - Page 220
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 198 Bus Cycles Chapter 7
  • AMD AMD-K6-2/400 | User Guide - Page 221
    logic must reset the AMD-K6-2E+ processor by asserting the RESET signal. When the processor samples RESET asserted, it immediately flushes and initializes all internal resources and its internal state, including its pipelines and caches, the floating-point state, the MMX and 3DNow! states, and all
  • AMD AMD-K6-2/400 | User Guide - Page 222
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 8.2 RESET Requirements During the initial power-on reset of the processor, RESET must remain asserted for a minimum of 1.0 ms after CLK and VCC reach specification. (See "CLK Switching Characteristics" on
  • AMD AMD-K6-2/400 | User Guide - Page 223
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Chapter 8 Table 35. Register State After RESET Register GDTR IDTR TR LDTR EIP EFLAGS EAX1 EBX ECX EDX2 ESI EDI EBP ESP CS SS DS ES FS GS FPU Stack R7-R03 FPU Control Word3 FPU Status Word3 FPU Tag Word3 FPU Instruction Pointer3 FPU
  • AMD AMD-K6-2/400 | User Guide - Page 224
    is non-zero, BIST failed. 2. EDX contains the AMD-K6-2E+ processor signature, where X indicates the processor Stepping ID. 3. The contents of these registers are preserved the falling transition of RESET. 6. Supported on low-power versions only. 202 Power-on Configuration and Initialization Chapter
  • AMD AMD-K6-2/400 | User Guide - Page 225
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 8.4 State of Processor After INIT The recognition of the assertion of INIT causes the processor to empty its pipelines, to initialize most of its internal state, and to branch to address FFFF_FFF0h-the same instruction execution
  • AMD AMD-K6-2/400 | User Guide - Page 226
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 204 Power-on Configuration and Initialization Chapter 8
  • AMD AMD-K6-2/400 | User Guide - Page 227
    architecture and resources of the AMD-K6-2E+ processor internal caches. The performance of the AMD-K6-2E+ processor is enhanced by writeback level-one (L1) and level-two (L2) caches. s The L1 cache is organized as separate 32-Kbyte instruction and data caches, each with two-way set associativity
  • AMD AMD-K6-2/400 | User Guide - Page 228
    AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 System Bus Interface Unit 32-Kbyte L1 Instruction Cache Tag Way 0 State Tag Way 1 State RAM Bit RAM Bit 64-Entry TLB Pre-Decode Instruction Cache 128-Entry TLB Tag Way 0 MESI Tag Way 1 MESI RAM Bits RAM
  • AMD AMD-K6-2/400 | User Guide - Page 229
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet L1 Instruction Cache Line Tag Cache Line 0 Byte 31 Predecode Bits Byte 30 Predecode Bits Byte 0 Predecode Bits 1 MESI Bit Address Cache Line 1 Byte 31 Predecode Bits
  • AMD AMD-K6-2/400 | User Guide - Page 230
    AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 9.2 Predecode Bits Decoding x86 instructions is particularly difficult because the instructions vary in length, ranging from 1 to 15 bytes long. Predecode logic supplies the predecode bits associated with each instruction
  • AMD AMD-K6-2/400 | User Guide - Page 231
    September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet The AMD-K6-2E+ processor does not enforce fault to occur. s When CD is set to 1 (disabled) and NW is set to 0, the cache fill mechanism is disabled but the contents of the cache are still valid. The processor
  • AMD AMD-K6-2/400 | User Guide - Page 232
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Table 36 describes how the PWT signal is driven based on the values of the Signal High Low Low Low Table 37 describes how the PCD signal is driven based on the values of the CD bit of CR0, the PCD bits, and
  • AMD AMD-K6-2/400 | User Guide - Page 233
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Table 38. CACHE# Signal Generation Cycle Type CI Bit of TR12 PCD accesses to the L1 and the L2 caches, the CD bit must be set to 1 and the caches must be completely flushed. There are three different
  • AMD AMD-K6-2/400 | User Guide - Page 234
    , if writing modified lines back to memory is not necessary, the INVD instruction can be used to invalidate all cache lines. s The third method for must be flushed and invalidated. The L2 cache in the AMD-K6-2E+ processor can be completely disabled by setting the L2 Disable (L2D) bit (EFER[4]) to 1
  • AMD AMD-K6-2/400 | User Guide - Page 235
    2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 9.5 L2 Cache Testing The AMD-K6-2E+ processor provides the L2AAR MSR uncacheable by the processor, then the memory access is assumed to be cacheable. Software can prevent caching of certain pages by setting the PCD bit in
  • AMD AMD-K6-2/400 | User Guide - Page 236
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Cache-line fills initiate 32-byte burst read cycles from memory on the system bus for the L1 instruction cache and the L1 data cache. All L1 cache-line fills supplied from the system bus are also filled in
  • AMD AMD-K6-2/400 | User Guide - Page 237
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 9.8 Chapter 9 L1 instruction-cache lines and L2 cache lines are replaced using a Least Recently Used (LRU) algorithm. If a line replacement is required, lines are replaced when read cache
  • AMD AMD-K6-2/400 | User Guide - Page 238
    one valid cache line in the sector. The two cache lines within a sector are guaranteed by design to be within the same page. The AMD-K6-2E+ processor uses two mechanisms that are programmable within the Write Handling Control Register (WHCR) to enable write allocations for write cycles that address
  • AMD AMD-K6-2/400 | User Guide - Page 239
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 63 32 31 22 21 17 16 15 0 is ((210-1) · 4 Mbytes) = 4092 Mbytes. When all the bits in this field are set to 0, all memory is above this limit and write allocates due to this mechanism is disabled (even
  • AMD AMD-K6-2/400 | User Guide - Page 240
    AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Sector" mechanisms). The WAE15M bit is ignored if the value in the WAELIM field is set to less than 16 Mbytes. By definition a write allocate is not performed in the memory area between 640 Kbytes and 1 Mbyte unless the processor
  • AMD AMD-K6-2/400 | User Guide - Page 241
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Chapter 9 The following list describes the corresponding items in Figure 85: 1. CD Bit of CR0-When the cache disable (CD) bit within control register 0 (CR0) is set to 1, the cache fill mechanism for both
  • AMD AMD-K6-2/400 | User Guide - Page 242
    negated. Wait states can also exist between burst cycles if the processor samples AHOLD or BOFF# asserted. The 3DNow! technology includes an instruction called PREFETCH that allows a cache line to be prefetched into the L1 data cache and the L2 cache. Unlike prefetching under hardware control
  • AMD AMD-K6-2/400 | User Guide - Page 243
    2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 9.10 Cache E = Exclusive, S = Shared, I = Invalid. The exclusive and shared states are indistinguishable in the L1 instruction cache and are treated as "valid" states. 2. The final MESI state assumes that the state of the WB
  • AMD AMD-K6-2/400 | User Guide - Page 244
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 5. This entry only applies to the L1 instruction cache. By design, a cache line cannot exist in the exclusive state in the L1 data cache and in the modified state in the L2 cache. 6. Assumes the write
  • AMD AMD-K6-2/400 | User Guide - Page 245
    L2 cache lines that are in the modified state and then marks all lines in the L1 instruction cache, the L1 data cache, and the L2 cache as invalid. The AMD-K6-2E+ processor contains the Page Flush/Invalidate Register (PFIR) that allows cache invalidation and optional flushing of a specific 4-Kbyte
  • AMD AMD-K6-2/400 | User Guide - Page 246
    AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 63 32 31 12 11 9 8 7 10 LINPAGE P F F / I Symbol LINPAGE PF F/I Reserved Description 20-bit Linear Page Address Page Fault in a page fault, the processor sets the PF bit to writebacks. These x86 instructions cause all cache
  • AMD AMD-K6-2/400 | User Guide - Page 247
    2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Table 40 shows Exclusive, S = Shared, I = Invalid. The exclusive and shared states are indistinguishable in the L1 instruction cache and are treated as "valid" states. 2. Writeback cycles to the bus are 32-byte burst writes
  • AMD AMD-K6-2/400 | User Guide - Page 248
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Table 41 shows burst writes. 3. This entry only applies to the L1 instruction cache. By design, a cache line cannot exist in the exclusive state in the L1 data cache and in the modified state in the L2 cache
  • AMD AMD-K6-2/400 | User Guide - Page 249
    and Writeback Coherency States The terms writethrough and writeback apply to two related concepts in a read-write cache like the AMD-K6-2E+ processor L1 data cache and the L2 cache. The following conditions apply to both the writethrough and writeback modes: s Memory Writes-A relationship exists
  • AMD AMD-K6-2/400 | User Guide - Page 250
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 s Writing to the Page Flush/Invalidate Register (PFIR) s The WBINVD instruction 228 Cache Organization Chapter 9
  • AMD AMD-K6-2/400 | User Guide - Page 251
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 10 10.1 Write Merge Buffer The AMD-K6-2E+ processor contains an 8-byte write merge buffer that allows the processor to conditionally combine data from multiple noncacheable write cycles into this merge
  • AMD AMD-K6-2/400 | User Guide - Page 252
    ™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 s EFER[3] is defined as the Global EWBE# Disable (GEWBED). When GEWBED equals 1, the processor does not attempt to enforce any write ordering internally or externally (the EWBE# signal is ignored). This is the maximum performance setting
  • AMD AMD-K6-2/400 | User Guide - Page 253
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 10.2 Table 42 summarizes the three settings of the EWBEC field for the EFER register, along with the effect of write ordering and performance. For more information on the EFER register, see "
  • AMD AMD-K6-2/400 | User Guide - Page 254
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 UC/WC Cacheability Control 63 49 48 34 33 32 31 17 16 2 10 Physical Base Address 1 WU Physical Address Mask 1 C C 11 Physical Base Address 0 WU Physical Address Mask 0 C C 00 MTRR1 MTRR0 Figure
  • AMD AMD-K6-2/400 | User Guide - Page 255
    AMD-K6™-2E+ Embedded Processor Data Sheet 10.3 WCn (n=0, 1). When set to 1, this memory range is defined as write combinable (see Table 43). Write-combinable memory is uncacheable. UCn (n=0, 1). When set physical base address must be aligned on a 128-Kbyte boundary. s The physical base address
  • AMD AMD-K6-2/400 | User Guide - Page 256
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Table 44 lists the valid physical address masks and the resulting range sizes that can be programmed in the UWCCR register. Table
  • AMD AMD-K6-2/400 | User Guide - Page 257
    2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 10.4 Examples Suppose set to 0 and bit 0 of the UWCCR register is set to 1 (UC0). s Extracting the 15 most-significant bits of the 32-bit physical base address that corresponds to 1 Gbyte (4000_0000h) yields a physical base
  • AMD AMD-K6-2/400 | User Guide - Page 258
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 236 Write Merge Buffer Chapter 10
  • AMD AMD-K6-2/400 | User Guide - Page 259
    Point and Multimedia Execution Units 11.1 Floating-Point Execution Unit The AMD-K6-2E+ processor contains an IEEE 754-compatible and 854-compatible floating-point execution unit designed to accelerate the performance of software that utilizes the x86 floating-point instruction set. Floating-point
  • AMD AMD-K6-2/400 | User Guide - Page 260
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 External Logic Support of Floating-Point Exceptions The processor provides the FERR# (Floating-Point Error) and IGNNE# (Ignore Numeric Error) signals to allow the external logic to generate the interrupt in
  • AMD AMD-K6-2/400 | User Guide - Page 261
    to enhance the performance of communications applications, including soft xDSL modems, MP3 recording, and Dolby Digital and Surround Sound processing. For more information on MMX instructions, see the AMD-K6® Processor Multimedia Technology Manual, order# 20726. For Chapter 11 Floating-Point and
  • AMD AMD-K6-2/400 | User Guide - Page 262
    Processor Data Sheet 23542A/0-September 2000 more information on 3DNow! instructions, see the 3DNow!™ Technology Manual, order# 21928. For more information on the 3DNow! technology DSP extensions, see the AMD Extensions to the 3DNow!™ and MMX™ Instructions Sets Manual, order# 22466. The multimedia
  • AMD AMD-K6-2/400 | User Guide - Page 263
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 12 System Management Mode (SMM) 12.1 SMM is an alternate operating mode entered by way of a system management interrupt (SMI#) and handled by an interrupt service routine. SMM is designed for system control
  • AMD AMD-K6-2/400 | User Guide - Page 264
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 s A20M# is masked s service routine is 0003_8000h. Fill Down SMM State-Save Area 0003_FFFFh 0003_FE00h 32-Kbyte Minimum RAM Service Routine Entry Point SMM Service Routine 0003_8000h SMM Base
  • AMD AMD-K6-2/400 | User Guide - Page 265
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Table 45 shows the initial state of registers shows the offsets in the SMM state-save area relative to the SMM base address. The SMM service routine can alter any of the read/write values in the state-save
  • AMD AMD-K6-2/400 | User Guide - Page 266
    Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September Base GS FS DS SS CS ES I/O Trap Doubleword No data dump at this address I/O Trap EIP1 No data dump at this address No data dump at this address IDT Base IDT Limit GDT Base GDT Limit TSS Attr TSS Base TSS Limit No data
  • AMD AMD-K6-2/400 | User Guide - Page 267
    and the extensions that are available on the processor. The SMM revision identifier fields are as follows: s Bits 31-18-Reserved s Bit 17-SMM base address relocation (1 = enabled) s Bit 16-I/O trap restart (1 = enabled) s Bits 15-0-SMM revision level for the AMD-K6-2E+ proces- sor= 0002h Chapter 12
  • AMD AMD-K6-2/400 | User Guide - Page 268
    Data Sheet 23542A/0-September 2000 12.4 12.5 246 Table 47 shows the format of the SMM Revision Identifier. Table 47. SMM Revision Identifier 31-18 Reserved 0 17 SMM Base Relocation 1 16 I/O Trap Extension 1 15-0 SMM Revision Level 0002h SMM Base Address During RESET, the processor sets
  • AMD AMD-K6-2/400 | User Guide - Page 269
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 12.6 Upon entry into SMM, state 0 = return to next instruction after the HLT instruction If the return from SMM takes the processor back to the Halt state, the HLT instruction is not re-executed, but the
  • AMD AMD-K6-2/400 | User Guide - Page 270
    Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 12.7 248 Table 48 shows the format of the I/O trap doubleword. Table 48. I/O Trap Doubleword Configuration 31-16 I/O Port Address 15-4 Reserved 3 REP String Operation 2 I/O String Operation 1 Valid I/O Instruction
  • AMD AMD-K6-2/400 | User Guide - Page 271
    into SMM never has bit 1 of the I/O trap doubleword set, and the second SMM service routine must not rewrite the I/O trap restart slot. During a simultaneous SMI# I/O instruction trap and debug breakpoint trap, the AMD-K6-2E+ processor first responds to the SMI# and postpones recognizing the debug
  • AMD AMD-K6-2/400 | User Guide - Page 272
    an SMI# I/O trap, the exception/interrupt priority of the AMD-K6-2E+ processor changes from its normal priority. The normal priority places the over debug traps. The processor recognizes the assertion of NMI within SMM immediately after the completion of an IRET instruction. Once NMI is recognized
  • AMD AMD-K6-2/400 | User Guide - Page 273
    Architecture (IEEE 1149.1-1990) specification. s Cache Inhibit-A feature that disables the processor's internal L1 and L2 caches. s Level-2 Cache Array Access Register (L2AAR)-The AMD-K6-2E+ processor provides the L2AAR that allows for direct access to the L2 cache and L2 tag arrays. s Debug Support
  • AMD AMD-K6-2/400 | User Guide - Page 274
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 13.2 252 The the BIST, the processor jumps to address FFFF_FFF0h to start instruction execution, regardless of the outcome of the BIST. The BIST takes approximately 5,000,000 processor clocks to complete.
  • AMD AMD-K6-2/400 | User Guide - Page 275
    processor. The AMD-K6-2E+ processor supports the TAP standard defined in the IEEE Standard Test Access Port and Boundary-Scan Architecture the IR. s Test Data Registers (TDR)-The three TDRs are used to process the test data. Each TDR is selected by an instruction in the Instruction Register (IR). See
  • AMD AMD-K6-2/400 | User Guide - Page 276
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 TAP Signals The test significant bit of all TAP registers, including the IR and all test data registers. Test data and instructions are serially shifted by one bit out of their respective registers on the
  • AMD AMD-K6-2/400 | User Guide - Page 277
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet TAP Registers Chapter 13 The AMD-K6-2E+ processor provides an Instruction Register (IR) and three Test Data Registers (TDR) to support the boundary-scan architecture. The IR and one of the TDRs-the Boundary-
  • AMD AMD-K6-2/400 | User Guide - Page 278
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 The total number of 1, and it is treated as an input if its enable bit equals 0. s If the current instruction is EXTEST, then the current state of each input pin is loaded. A bidirectional pin is treated
  • AMD AMD-K6-2/400 | User Guide - Page 279
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Table 50. Boundary Scan Bit D57 103 D15_E 267 BE0_E 234 A29 201 EADS# 168 STPCLK# 135 D5_E 102 D15 266 BE0# 233 WR_E 200 BE2_E 167 BF2 134 D5 101 D37_E 265 BE5_E 232 W/R# 199 BE2# 166 KEN#
  • AMD AMD-K6-2/400 | User Guide - Page 280
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Table 50. bits. 2. Supported on low-power versions only. Device Identification Register (DIR). The DIR is a 32-bit Test Data Register selected during the execution of the IDCODE instruction. The fields
  • AMD AMD-K6-2/400 | User Guide - Page 281
    the AMD-K6-2E+ processor. TAP Instructions The processor supports the three instructions required by the IEEE 1149.1 standard - EXTEST, SAMPLE/PRELOAD, and BYPASS - as well as two additional optional instructions - IDCODE and HIGHZ. Table 52 shows the complete set of TAP instructions supported by
  • AMD AMD-K6-2/400 | User Guide - Page 282
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 TAP Controller State Machine EXTEST Instruction. When the EXTEST instruction is executed, the processor loads the BSR shift register with the current state of the input and bidirectional pins in the Capture-
  • AMD AMD-K6-2/400 | User Guide - Page 283
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Test-Logic-Reset 1 0 Run-Test/Idle 1 0 0 1 Select-DR-Scan 0 Capture-DR 0 Shift-DR 1 Exit1-DR 1 1 1 Select-IR-Scan 1 0 Capture-IR 0 Shift-IR 0 1 1 Exit1-IR 0 Pause-
  • AMD AMD-K6-2/400 | User Guide - Page 284
    AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 The states of the TAP controller are described as follows: Test-Logic-Reset. This state represents the initial reset state of the TAP controller and is entered when the processor the EXTEST instruction, the processor loads the BSR
  • AMD AMD-K6-2/400 | User Guide - Page 285
    shifting process of a Test Data Register. s Pause-IR-This state is entered to temporarily stop the shifting process of the Instruction Register. s Exit2-DR Inhibit The AMD-K6-2E+ processor provides a means for inhibiting the normal operation of its internal L1 and L2 caches while still supporting an
  • AMD AMD-K6-2/400 | User Guide - Page 286
    the INVD instruction (modified cache lines are not written back to memory) s Using the Page Flush/Invalidate Register (PFIR) (see "Page Flush/Invalidate Register (PFIR)" on page 223) 13.5 L2 Cache and Tag Array Testing Level-2 Cache Array Access Register (L2AAR) The AMD-K6-2E+ processor provides
  • AMD AMD-K6-2/400 | User Guide - Page 287
    2 Way 3 512 sets Set 511 Figure 91. L2 Cache Organization for AMD-K6™-2E+ Processor Octet 0 Octet 1 cache is a function of the instruction executed-RDMSR or WRMSR-and the data or tags (refer to Figure 93 on page 266). Bit 20 of EDX (T/D) determines whether the access is to the L2 cache data
  • AMD AMD-K6-2/400 | User Guide - Page 288
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 page 266 describes the operation that is performed based on the instruction and the T/D bit. Symbol Description T/D Selects Tag (1) or Data (0) access Way Selects desired cache way Bit 20 17-16 31 21 20
  • AMD AMD-K6-2/400 | User Guide - Page 289
    0 state (M=11, E=10, S=01, I=00) 9-8 LRU Two bits of LRU for each way 7-0 Figure 95. L2 Tag Information for the AMD-K6™-2E+ Processor-EAX LRU (Least Recently Used). For the 4-way set associative L2 cache, each way has a 2-bit LRU field for each sector. Values for the LRU field are 00b, 01b, 10b
  • AMD AMD-K6-2/400 | User Guide - Page 290
    Recent Than 01b 11b Least Recently Used Figure 96. LRU Byte Debug The AMD-K6-2E+ processor implements the standard x86 debug functions, registers, and exceptions. In addition, the processor supports the I/O breakpoint debug extension. The debug feature assists programmers and system designers during
  • AMD AMD-K6-2/400 | User Guide - Page 291
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Debug Registers Figures 97 through 100 show the 32-bit debug registers supported by the processor. Symbol LEN 3 R/W 3 LEN 2 R/W 2 LEN 1 R/W 1 LEN 0 R/W 0 Description Bits Length of Breakpoint #3 31-30
  • AMD AMD-K6-2/400 | User Guide - Page 292
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  • AMD AMD-K6-2/400 | User Guide - Page 293
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet DR3 31 30 29 28 27 26 25 24 Figure 100. Debug Registers DR3, DR2, DR1, and DR0 DR3-DR0. The processor allows the setting of up to four breakpoints. DR3-DR0 contain the linear addresses for breakpoint 3
  • AMD AMD-K6-2/400 | User Guide - Page 294
    Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 extensions are enabled (bit 3 of CR4 is set to the EFLAGS register is set to 1, the processor generates a debug exception after the successful execution of every instruction (single-step operation) and sets the BS bit (
  • AMD AMD-K6-2/400 | User Guide - Page 295
    2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Debug Exceptions The LE (bit 8) and GE (bit 9) bits in DR7 have no effect on the operation of the processor and are provided in order to be software-compatible with previous generations of x86 processors. When set to 1, the
  • AMD AMD-K6-2/400 | User Guide - Page 296
    debug faults that cause the processor to generate an Interrupt 01h exception: s Enabled breakpoints for instruction execution s BD bit in DR6 set to 1 Interrupt 03h. The INT 3 instruction is defined in the x86 architecture as a breakpoint instruction. This instruction causes the processor to
  • AMD AMD-K6-2/400 | User Guide - Page 297
    September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 14 Clock Control 14.1 Clock Control States The standard-power versions of the AMD-K6-2E+ processor support five modes of clock control. The low-power versions of the AMD-K6-2E+ processor support six modes of clock
  • AMD AMD-K6-2/400 | User Guide - Page 298
    clock control state transitions on the standard-power and low-power versions, respectively, of the AMD-K6-2E+ processor. Each of the reduced-power states are described in the following sections. HLT Instruction RESET, SMI#, INIT, or INTR Asserted Normal Mode - Real - Virtual-8086 - Protected - SMM
  • AMD AMD-K6-2/400 | User Guide - Page 299
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet HLT Instruction RESET, SMI#, INIT, or INTR Asserted Normal Mode - Real - Virtual-8086 - Protected - SMM Non-zero value written to SGTC SGTC timer expires STPCLK# Asserted STPCLK#
  • AMD AMD-K6-2/400 | User Guide - Page 300
    input signals apply within the Halt state. 14.3 Stop Grant State Enter Stop Grant State 278 After recognizing the assertion of STPCLK#, the AMD-K6-2E+ processor flushes its instruction pipelines, completes all pending and in-progress bus cycles, and acknowledges the Clock Control Chapter 14
  • AMD AMD-K6-2/400 | User Guide - Page 301
    state in that the processor disables most of its internal clock distribution in the Stop Grant state. In order to support the following operations, the to returning to the Normal state, the AMD-K6-2E+ processor guarantees that a minimum of one instruction is executed prior to re-entering the Stop
  • AMD AMD-K6-2/400 | User Guide - Page 302
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 processor latches the edge-sensitive signals (INIT, FLUSH#, NMI, and SMI#), but otherwise does not exit the Stop Grant state to service the interrupt. When the processor returns to the Normal state due to
  • AMD AMD-K6-2/400 | User Guide - Page 303
    supported on the low-power versions of the AMD-K6-2E+ processor. After receiving a write of a non-zero value to the SGTC (Stop Grant Time-out Counter) field located within the EPM 16-byte I/O block, the processor flushes its instruction the VIDC bit is set to 1. s Forwards the processor-to-bus clock
  • AMD AMD-K6-2/400 | User Guide - Page 304
    Data Sheet 23542A/0-September 2000 If INIT, INTR (if interrupts are enabled), FLUSH#, NMI, or SMI# are sampled asserted in the EPM Stop Grant state, the processor latches the edge-sensitive signals (INIT, FLUSH#, NMI, and SMI#), but otherwise does not exit the EPM Stop Grant state to service
  • AMD AMD-K6-2/400 | User Guide - Page 305
    unchanged in the Stop Clock state. Exit Stop Clock State The AMD-K6-2E+ processor returns to the Stop Grant state from the Stop Clock state after a minimum of 1.0 ms. The frequency of CLK when exiting the Stop Clock state can be different than the frequency of CLK when entering the Stop Clock
  • AMD AMD-K6-2/400 | User Guide - Page 306
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 284 Clock Control Chapter 14
  • AMD AMD-K6-2/400 | User Guide - Page 307
    Information AMD-K6™-2E+ Embedded Processor Data Sheet 15 Electrical Data This chapter includes specifications for the operating ranges, absolute ratings, and DC characteristics of the AMD-K6-2E+ embedded processor. Nominal and maximum power dissipation values for the AMD-K6-2E+ processor during
  • AMD AMD-K6-2/400 | User Guide - Page 308
    (Minimum)3 TCASE Case Temperature (Maximum)5 400 MHz 450 MHz 1.9 V 2.0 V 2.1 V 3.135 V 3.30 V 3.6 V 0•C 70•C 500 MHz Notes: 1. VCC2 and VCC3 are referenced from VSS. 2. VCC2 specification for 2.0-V component 3. Case temperature range required for AMD-K6-2E+/xxxyACR valid ordering part number
  • AMD AMD-K6-2/400 | User Guide - Page 309
    of the AMD-K6-2E+ processor are shown in Table 58. Table 58. DC Characteristics for the AMD-K6™-2E+ Processor Symbol Parameter Data Min -0.3 V Max +0.8 V 2.0 V VCC3+0.3 V 0.4 V 2.4 V 5.30 A 6.15 A 7.60 A Comments IOL = 4.0-mA load IOH = 3.0-mA load 350 MHz2,3 400 MHz2,3,4 450
  • AMD AMD-K6-2/400 | User Guide - Page 310
    (TDO) TCK Capacitance Preliminary Data Min Max 8.70 A 9.25 A 9.75 A 0.64 A 0.65 A 0.66 A 0.68 A –15 mA –15 mA -500 mA 500 mA 10 pF 15 pF 20 pF 10 pF 10 pF 15 pF 10 pF Comments 400 MHz3,4,5 450 MHz3,5 500 MHz3,5 350 MHz3,6 400 MHz3,4,6 450 MHz3,6 500 MHz3,6 Notes: 1. VCC3 refers
  • AMD AMD-K6-2/400 | User Guide - Page 311
    supported voltages and operating frequencies for low-power versions of AMD-K6-2E+ processors enabled with AMD PowerNow! technology. Table 59. Power Dissipation for Low-Power AMD-K6™-2E+ Devices Power Dissipation 350 MHz1 400 MHz1,2 450 MHz1 Active3 Application Power AMD PowerNow! Technology
  • AMD AMD-K6-2/400 | User Guide - Page 312
    + Processors Enabled with AMD PowerNow!™ Technology Ordering Part Number1 AMD-K6-2E+/450APZ AMD-K6-2E+/400xTZ AMD-K6-2E+/350xUZ Core Voltage 1.7 V 1.6 V 1.5 V 1.4 V 1.6 V 1.5 V 1.4 V 1.5 V 1.4 V Range of Supported Operating Frequencies2 450-200 MHz 400-200 MHz 350-200 MHz 300-200 MHz 400-200 MHz
  • AMD AMD-K6-2/400 | User Guide - Page 313
    on page 292.) In order to maintain a low-impedance current sink and reference, the ground plane must never be split. Although the AMD-K6-2E+ processor has two separate supply voltages, there are no special power sequencing requirements. The best procedure is to minimize the time between which VCC2
  • AMD AMD-K6-2/400 | User Guide - Page 314
    be used under the processor's ZIF socket to minimize resistance and inductance in the lead lengths while maintaining minimal height. For information and recommendations about the specific value, quantity, and location of the capacitors, see the AMD-K6® Processor Power Supply Design Application
  • AMD AMD-K6-2/400 | User Guide - Page 315
    2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Pin Connection Requirements For proper operation, the following requirements for signal pin connections must be met: s Do not drive address and data signals into large capacitive loads at high frequencies. If necessary, use
  • AMD AMD-K6-2/400 | User Guide - Page 316
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 294 Electrical Data Chapter 15
  • AMD AMD-K6-2/400 | User Guide - Page 317
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 16 Signal Switching Characteristics The AMD-K6-2E+ processor signal to input and output signals that are switching from Low to High, or from High to Low s Based on input signals applied at a slew rate of 1 V/ns between 0 V and 3 V (
  • AMD AMD-K6-2/400 | User Guide - Page 318
    clock skew between the AMD-K6-2E+ processor and the system logic. 16.2 Clock Switching Characteristics for 100-MHz Bus Operation Table 62. CLK Switching Characteristics for 100-MHz Bus Operation Symbol Parameter Description Preliminary Data Min Max Figure Comments Frequency t1 CLK Period
  • AMD AMD-K6-2/400 | User Guide - Page 319
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 16.3 Clock Switching Characteristics for 66-MHz Bus Operation Table 63. CLK Switching Characteristics for 66-MHz Bus Operation Symbol Parameter Description Frequency t1 CLK Period t2 CLK High Time t3
  • AMD AMD-K6-2/400 | User Guide - Page 320
    logic to assure the proper operation of the AMD-K6-2E+ processor. s The setup and hold timings during functional and boundary-scan test mode are given relative to the rising edge of CLK and TCK, respectively. 16.5 Output Delay Timings for 100-MHz Bus Operation Table 64. Output Delay Timings for
  • AMD AMD-K6-2/400 | User Guide - Page 321
    September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Table 64. Output Delay Timings for 100-MHz Bus Operation (continued) Symbol Parameter Description t19 CACHE# Float Delay t20 D/C# Valid Delay t21 D/C# Float Delay t22 D[63:0] Write Data Valid Delay t23 D[63
  • AMD AMD-K6-2/400 | User Guide - Page 322
    Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 16.6 Input Setup and Hold Timings for 100-MHz Bus Operation Table 65. Input Setup and Hold Timings for 100-MHz Bus 108 108 108 108 108 108 108 108 108 108 108 300 Signal Switching Characteristics Chapter 16
  • AMD AMD-K6-2/400 | User Guide - Page 323
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Table 65. Input Setup and Hold Timings for 100-MHz Bus Operation (continued) Symbol Parameter Description Preliminary Data Min Max Figure t732 INIT Hold Time 1.0 ns 108 t741 INTR Setup Time t751
  • AMD AMD-K6-2/400 | User Guide - Page 324
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 16.7 Output Delay Timings for 66-MHz Bus Operation Table 66. Output Delay Timings for 66-MHz Bus Operation Symbol Parameter Description t6 A[31:3] Valid Delay t7 A[31:3] Float Delay t8 ADS# Valid
  • AMD AMD-K6-2/400 | User Guide - Page 325
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Table 66. Output Delay Timings for 66-MHz Bus Operation (continued) Symbol Parameter Description t36 PCHK# Valid Delay t37 PWT Valid Delay t38 PWT Float Delay t39 SCYC Valid Delay t40 SCYC Float
  • AMD AMD-K6-2/400 | User Guide - Page 326
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 16.8 Input Setup and Hold Timings for 66-MHz Bus Operation Table 67. Input Setup and Hold Timings for 66-MHz Bus Operation Symbol Parameter Description t44 A[31:5] Setup Time t45 A[31:5] Hold Time
  • AMD AMD-K6-2/400 | User Guide - Page 327
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Table 67. Input Setup and Hold Timings for 66-MHz Bus Operation (continued) Symbol Parameter Description Preliminary Data Min Max Figure t732 INIT Hold Time 1.0 ns 108 t741 INTR Setup Time t751
  • AMD AMD-K6-2/400 | User Guide - Page 328
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 16.9 RESET and Test Signal Timing Table 68. RESET and Configuration Signals for 100-MHz Bus Operation Symbol Parameter Description Preliminary Data Min Max Figure t90 RESET Setup Time 1.7 ns 109
  • AMD AMD-K6-2/400 | User Guide - Page 329
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Table 69. RESET and Configuration Signals for 66-MHz Bus Operation Symbol Parameter Description Preliminary Data Min Max Figure t90 RESET Setup Time 5.0 ns 109 t91 RESET Hold Time 1.0 ns 109 t92
  • AMD AMD-K6-2/400 | User Guide - Page 330
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Table 70. TCK Waveform and TRST# Timing at 25 MHz Symbol Parameter Description Preliminary Data Min Max TCK Frequency 25 MHz t103 TCK Period t104 TCK High Time t105 TCK Low Time 40.0 ns 14.0 ns
  • AMD AMD-K6-2/400 | User Guide - Page 331
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 16.10 Timing Diagrams WAVEFORM INPUTS Must be steady OUTPUTS Steady Can change from High to Low Changing from High to Low Can change from
  • AMD AMD-K6-2/400 | User Guide - Page 332
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Tx CLK 1.5 V Output Signal Tx Max Input Signal Tx Tx Tx Tx 1.5 V ts th Note: For symbols ts and th listed in Table 65 on page 300 and Table 67 on page 304, where: s = 44, 46, 48, 50, 52, 54, 56, 58,
  • AMD AMD-K6-2/400 | User Guide - Page 333
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet CLK RESET Tx t90 1.5 V FLUSH# (Synchronous) FLUSH# (Asynchronous) BF[2:0] (Asynchronous) • • • Tx 1.5 V • • • t92, 93 t91 1.5 V t99 t100 • • • • • • t 101 t 102 • • • t94 t95 Figure 109. Reset and
  • AMD AMD-K6-2/400 | User Guide - Page 334
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 t104 2.0 V 1.5 V 0.8 V t107 Figure 110. TCK Waveform t105 t106 t103 t108 1.5 V Figure 111. TRST# Timing TCK TDI, TMS TDO Output Signals t103 1.5 V t109,
  • AMD AMD-K6-2/400 | User Guide - Page 335
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 17 Thermal Design 17.1 Package Thermal Specifications The AMD-K6-2E+ processor operating specification calls for the case temperature (TC) to be in the range of 0°C to 70°C for standard-power devices and
  • AMD AMD-K6-2/400 | User Guide - Page 336
    Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Table 72. Package Thermal Specification for Low-Power AMD-K6™-2E+ Devices qJC Junction-Case 1.0° C/W Stop Grant Mode Stop Clock Mode TC Case Temperature Maximum Thermal Power 350 MHz 7.50 W 400 MHz 9.50 W 450 MHz 12
  • AMD AMD-K6-2/400 | User Guide - Page 337
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Temperature (Ambient) Thermal Resistance (°C/W) TCA Sink Case qSA qCA qIF Figure 113. Thermal Model (CPGA Package) Figure 114 illustrates the case-to-ambient temperature (TCA)
  • AMD AMD-K6-2/400 | User Guide - Page 338
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 The thermal resistance of a by the processor is transferred from the top surface of the case. The small amount of heat generated from the bottom side of the processor where the processor socket blocks the
  • AMD AMD-K6-2/400 | User Guide - Page 339
    AMD-K6™-2E+ Embedded Processor Data Sheet 17.2 Measuring Case Temperature The processor case temperature is measured to ensure that the thermal solution meets the processor drilled through the heatsink base (for example, 1/16 of an inch). Secure the thermocouple to the base of the heatsink by
  • AMD AMD-K6-2/400 | User Guide - Page 340
    AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 voltage regulator placed parallel to the processor with the airflow aligned with the devices. With this alignment, the heat generated by the voltage regulator has minimal effect on the processor. Voltage Regulator Processor
  • AMD AMD-K6-2/400 | User Guide - Page 341
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Airflow Ideal areas for voltage regulator Figure 118. Airflow for a Heatsink with Fan Airflow Management in a System Design Complete airflow management in a system is important. In addition to the volume
  • AMD AMD-K6-2/400 | User Guide - Page 342
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Figure 120 shows the airflow management in a system using the ATX form-factor. The orientation of the power supply fan and the motherboard are modified in the ATX platform design. The power supply fan pulls
  • AMD AMD-K6-2/400 | User Guide - Page 343
    /0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 18 Pin Designations This chapter ) Pins RSVD (Reserved) Pins Note that the OBGA package includes additional pins not supported on the CPGA package. Table 74 shows the pin differences between the two packages.
  • AMD AMD-K6-2/400 | User Guide - Page 344
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 18.1 Pins Designations for CPGA Package Data Pins B D F W Y AA AC AE AG AJ AL AN Notes: The VID[4:0] outputs are supported on low-power versions only. These pins are defined as no-connects on standard-power
  • AMD AMD-K6-2/400 | User Guide - Page 345
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 27 28 29 30 31 32 33 34 35 36 37 Notes: The VID[4:0] outputs are supported on low-power versions only. These pins are defined as no-connects on standard-power versions.
  • AMD AMD-K6-2/400 | User Guide - Page 346
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Table 75. CPGA Pin Designations 25 R-34 AN-35 AH-32 Notes: 1. The VID[4:0] pins are supported on low-power versions only. These pins are defined as no-connects on standard-power versions. 324 Pin Designations
  • AMD AMD-K6-2/400 | User Guide - Page 347
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Table 76. CPGA Pin Designations for No Connect, Reserved, Power, and Ground Pins No Connect (NC) A-37 C-01 E-171 E-251 R-341 S-33 S-35 W-33 AH-
  • AMD AMD-K6-2/400 | User Guide - Page 348
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 18.2 Pins Designations for OBGA Package 1 corner of the OBGA package due to manufacturing requirements. The VID[4:0] outputs are supported on low-power versions only. These pins are defined as no-connects on
  • AMD AMD-K6-2/400 | User Guide - Page 349
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet A B C D E F G H J K L MN P R T U VW 1 DP6 corner of the OBGA package due to manufacturing requirements. The VID[4:0] outputs are supported on low-power versions only. These pins are defined as no-connects on
  • AMD AMD-K6-2/400 | User Guide - Page 350
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Table 77. OBGA Pin Designations by VID2 L19 VID3 C15 VID4 A11 Notes: 1. The VID[4:0] pins are supported on low-power versions only. These pins are defined as no-connects on standard-power versions.
  • AMD AMD-K6-2/400 | User Guide - Page 351
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Table 78. OBGA Pin Designations for No Connect, No Connect (INC) H7 K14 E8 M5 N16 J5 L15 E9 M12 Reserved (RSVD) K6 M14 E10 M13 G1 K7 N15 E11 M15 G3 K8 N18 E12 N2 G16 K9 P11
  • AMD AMD-K6-2/400 | User Guide - Page 352
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 330 Pin Designations Chapter 18
  • AMD AMD-K6-2/400 | User Guide - Page 353
    23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 19 Package Specifications 19.1 321-Pin Staggered CPGA Package Specification Figure 125. 321-Pin Staggered CPGA Package Specification Chapter 19 Package Specifications 331
  • AMD AMD-K6-2/400 | User Guide - Page 354
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 19.2 349-Ball OBGA Package Specification 23542A/0-September 2000 Dwg rev. AA.04; 08/00 Figure 126. 349-Ball OBGA Package Specification 332 Package Specifications Chapter 19
  • AMD AMD-K6-2/400 | User Guide - Page 355
    AMD-K6™-2E+ Embedded Processor Data Sheet 20 Ordering Information Standard AMD-K6-2E+ Embedded Processor Products AMD V (Core)/ 3.135 V-3.6 V (I/O) Package Type A = 321-pin CPGA I = 349-ball OBGA Performance Rating /500 /400 /450 /350 Family/Core AMD-K6-2E+ Chapter 20 Ordering Information 333
  • AMD AMD-K6-2/400 | User Guide - Page 356
    Table 79. AMD-K6™-2E+ Embedded Processor Valid Ordering Part Number Combinations Device Type OPN1 Package Type Operating Voltage Case Maximum CPU/Bus Temperature Frequency AMD-K6-2E+/350AUZ 321-pin CPGA 1.4 V-1.6 V (Core) 3.135 V-3.6 V (I/O) 0°C - 85°C 350 MHz/100 MHz AMD-K6-2E+/400ATZ
  • AMD AMD-K6-2/400 | User Guide - Page 357
    2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Index Numerics 0.18-Micron Process Technology 7 100-MHz Bus clock switching characteristics 296 frontside 1, 8 input setup and hold timings 300 output delay timings 298 Super7 platform support 1, 8 321-Pin Staggered
  • AMD AMD-K6-2/400 | User Guide - Page 358
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 coherency 222 external 214 data reads 266 direct access 50 disabling for debug 47 EDX register content 265 Level-2 Cache Array Access Register (L2AAR 50 organization 205 RDMSR instruction effect
  • AMD AMD-K6-2/400 | User Guide - Page 359
    MMX, and 3DNow! Instructions 240 Component Placement 292 Configuration power-on initialization 199 signal timing (figure 311 signal timing for 100-MHz bus operation (table 306 signal timing for 66-MHz bus operation 307 VCC pins 200 CR4 Register 46 Customer Service iii Cycles bus 153 hold
  • AMD AMD-K6-2/400 | User Guide - Page 360
    , 240 Float Conditions 136, 141 Floated signal 93 Floating-Point and MMX/3DNow! instruction compatibility 240 and multimedia execution units 237 error 111 execution unit 237 handling exceptions 237 instructions (table 82 register data types 34 registers 31 FLUSH# Signal 112, 199, 223, 252
  • AMD AMD-K6-2/400 | User Guide - Page 361
    integer (table 65 INVD 224 MMX technology 86, 239 MMX technology (table 86 pointer 31 PREFETCH 17, 220 RSM 241 serializing 94 supported by the processor (table 63 Test Access Port (TAP 259 WBINVD 224 Integer data registers 29 data types 29 instructions (table 65 Interrupts 130, 188
  • AMD AMD-K6-2/400 | User Guide - Page 362
    Array Access Register (L2AAR). . . . . 264-266 Literature iii LOCK# Signal 120 Locked cycles 184 operation with BOFF MMX Technology 19, 21-24, 127 3DNow!™ registers 35 data types 37 exceptions 240 INIT state 203 instruction compatibility, floating-point and 240 instructions 240 instructions
  • AMD AMD-K6-2/400 | User Guide - Page 363
    AMD-K6™-2E+ Embedded Processor Data Sheet Operating Ranges 285 OPN 333 Ordering Information 333 Ordering Part Number (OPN 333 Output delay timings 100-MHz bus operation 298 66-MHz bus operation 302 leakage current 288 pin float conditions (table 141 signal state after RESET (table 200
  • AMD AMD-K6-2/400 | User Guide - Page 364
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Real Mode INIT-initiated transition 196 protected mode transition 196 Register X and Y functional unit 24 pipelines 24 Registers 14, 27, 240 3DNow!™ technology 35 boundary scan (BSR 255 bypass (BR 259
  • AMD AMD-K6-2/400 | User Guide - Page 365
    /0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet HITM 113 HLDA 114 HOLD 115 IGNNE 116, 240 INIT 117, 278, 281 INTR 118, 278, 281 INV 118 KEN 119 LOCK 120 logic symbol (figure 91 M/IO 121 NA 122 negated 93 NMI 123, 278, 281 output 200 PCD 124 PCHK
  • AMD AMD-K6-2/400 | User Guide - Page 366
    AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 System Management Mode (SMM 241 AMD PowerNow!™ features 145 base iii Technical Support iii Temperature identification (DIR 258 instruction register (IR . . 200, 202, 210 Uncacheable Memory 49, 230-231 UWCCR 49, 200, 202,
  • AMD AMD-K6-2/400 | User Guide - Page 367
    AMD-K6™-2E+ Embedded Processor Data Sheet power connections 291 RESET requirements 200 W W/R# Signal 138 WB/WT# Signal 139 WBINVD Instruction 224 WC Memory Type 49 WHCR 44, 48, 202 EWBEC settings (table 231 memory type range registers (MTRRs 231 memory-range restrictions 233 examples 235
  • AMD AMD-K6-2/400 | User Guide - Page 368
    Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 346 Index
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Preliminary Information
AMD-K6™-2E+
Embedded Processor
Data Sheet
Publication #
23542
Rev:
A
Amendment/
0
Issue Date:
September 2000