AMD AMD-K6-2/400 User Guide - Page 134

Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 5.23 FLUSH# (Cache Flush) Pin Attribute Input Summary In response to sampling FLUSH# asserted, the processor writes back any cache lines in the L1 data cache or L2 cache that are in the modified state, invalidates all lines in the L1 and L2 caches, and then executes a flush acknowledge special cycle. See Table 24 on page 142 for the bus definition of special cycles. In addition, FLUSH# is sampled when RESET is negated to determine if the processor enters the Three-State Test mode. If FLUSH # is 0 during the falling transition of RESET, the processor enters the Three-State Test mode instead of performing the normal RESET functions. Sampled FLUSH # is sampled and latched as a falling edge-sensitive signal. During normal operation (not RESET), FLUSH # is sampled on every clock edge but is not recognized until the next instruction boundary. s If FLUSH# is asserted synchronously (see Table 19 on page 140), it can be asserted for a minimum of one clock. s If FLUSH# is asserted asynchronously, it must have been negated for a minimum of two clocks, followed by an assertion of a minimum of two clocks. FLUSH# is also sampled during the falling transition of RESET. If RESET and FLUSH# are driven synchronously, FLUSH# is sampled on the clock edge prior to the clock edge on which RESET is sampled negated. If RESET is driven asynchronously, the minimum setup and hold time for FLUSH#, relative to the negation of RESET, is two clocks. 112 Signal Descriptions Chapter 5