AMD AMD-K6-2/400 User Guide - Page 181
Bus Cycles,
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23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Figure 60, the second write cycle occurs during the execution of a serializing instruction. The processor delays the following cycle until EWBE# is sampled asserted. CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# BREQ D[63:0] DP[7:0] CACHE# EWBE# KEN# BRDY# WB/WT# Read Cycle Write Cycle Write Cycle (Next Cycle Delayed by EWBE#) ADDR DATA IDLE ADDR DATA DATA IDLE ADDR DATA DATA IDLE IDLE IDLE IDLE IDLE ADDR Figure 60. Non-Pipelined Single-Transfer Memory Read/Write and Write Delayed by EWBE# Chapter 7 Bus Cycles 159
Chapter 7
Bus Cycles
159
23542A/0—September 2000
AMD-K6™-2E+ Embedded Processor Data Sheet
Preliminary Information
Figure 60, the second write cycle occurs during the execution of
a serializing instruction. The processor delays the following
cycle until EWBE# is sampled asserted.
Figure 60.
Non-Pipelined Single-Transfer Memory Read/Write and Write Delayed by EWBE#
Read Cycle
Write Cycle (Next Cycle Delayed by EWBE#)
Write Cycle
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
BREQ
D[63:0]
DP[7:0]
CACHE#
EWBE#
KEN#
BRDY#
WB/WT#
ADDR
DATA
IDLE
ADDR
ADDR
DATA
IDLE
DATA
DATA
DATA
IDLE
IDLE
IDLE
IDLE
IDLE
ADDR