AMD AMD-K6-2/400 User Guide - Page 53

23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Physical Memory Segment Register Real Mode Memory Model Descriptor Table Base Limit Base Base Limit Segment Base Physical Memory Segment Selector Segment Base Figure 10. Segment Usage Protected Mode Memory Model Instruction Pointer Floating-Point Registers The instruction pointer (EIP or IP) is used in conjunction with the code segment register (CS). The instruction pointer is either a 32-bit register (EIP) or a 16-bit register (IP) that keeps track of where the next instruction resides within memory. This register cannot be directly manipulated, but can be altered by modifying return pointers when a JMP or CALL instruction is used. The floating-point execution unit in the AMD-K6-2E+ processor is designed to perform mathematical operations on non-integer numbers. This floating-point unit conforms to the IEEE 754 and 854 standards and uses several registers to meet these standards - eight numeric floating-point registers, a status word register, a control word register, and a tag word register. Chapter 3 Software Environment 31