AMD AMD-K6-2/400 User Guide - Page 162
Pin Tables by Type, Signal Descriptions,
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Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 5.56 Pin Tables by Type Table 19. Input Pin Types Name Type Name Type A20M#1 AHOLD BF[2:0]3 BOFF# BRDY# BRDYC# CLK EADS# EWBE#6 FLUSH#2,7 HOLD Asynchronous Synchronous Synchronous Synchronous Synchronous Synchronous Clock Synchronous Synchronous Asynchronous Synchronous IGNNE#1 INIT2 INTR1 INV KEN# NA# NMI2 RESET4,5 SMI#2 STPCLK#1 WB/WT# Asynchronous Asynchronous Asynchronous Synchronous Synchronous Synchronous Asynchronous Asynchronous Asynchronous Asynchronous Synchronous Notes: 1. These level-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks. 2. These edge-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and must remain asserted at least two clocks. 3. BF[2:0] are sampled during the falling transition of RESET. They must meet a minimum setup time of 1.0 ms and a minimum hold time of two clocks relative to the negation of RESET. 4. During the initial power-on reset of the processor, RESET must remain asserted for a minimum of 1.0 ms after CLK and VCC reach specification before it is negated. 5. During a warm reset, while CLK and VCC are within their specification, RESET must remain asserted for a minimum of 15 clocks prior to its negation. 6. When register bit EFER[3] is set to 1, EWBE# is ignored by the processor. 7. FLUSH# is also sampled during the falling transition of RESET and can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold times must be met relative to the clock edge before the clock edge on which RESET is sampled negated. If asserted asynchronously, FLUSH# must meet a minimum setup and hold time of two clocks relative to the negation of RESET. 140 Signal Descriptions Chapter 5