AMD AMD-K6-2/400 User Guide - Page 41
Parallel Short Decoders., AMD-K6™-2E+ Processor Decode Logic
View all AMD AMD-K6-2/400 manuals
Add to My Manuals
Save this manual to your list of manuals |
Page 41 highlights
23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet operation - a register-to-register add. More complex x86 instructions are decoded into several RISC86 operations. Instruction Buffer On-Chip ROM Short Decoder #1 Short Decoder #2 Long Decoder Vector Decoder RISC86® Sequencer Vector Address 4 RISC86 Operations Figure 4. AMD-K6™-2E+ Processor Decode Logic The AMD-K6-2E+ processor uses a combination of decoders to convert x86 instructions into RISC86 operations. The hardware consists of three sets of decoders-two parallel short decoders, one long decoder, and one vector decoder. Parallel Short Decoders. The two parallel short decoders translate the most commonly-used x86 instructions ( moves, shifts, branches, ALU, FPU) and the extensions to the x86 instruction set (including MMX and 3DNow! instructions) into zero, one, or two RISC86 operations each. The short decoders only operate on x86 instructions that are up to seven bytes long. In addition, Chapter 2 Internal Architecture 19