AMD AMD-K6-2/400 User Guide - Page 234
L2 Cache Disabling, the Flush/Invalidate Register PFIR, which allows
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Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 L2 Cache Disabling the modified state, invalidates all lines in all caches, and then executes a flush acknowledge special cycle (See Table 24 on page 142). s The second method for flushing the caches is for software to execute the WBINVD instruction, which causes all modified lines to first be written back to memory, then marks all cache lines as invalid. Alternatively, if writing modified lines back to memory is not necessary, the INVD instruction can be used to invalidate all cache lines. s The third method for flushing the caches is to make use of the Page Flush/Invalidate Register (PFIR), which allows cache invalidation and optional flushing of a specific 4Kbyte page from the linear address space (see "Page Flush/Invalidate Register (PFIR)" on page 223). Unlike the previous two methods of flushing the caches, this particular method requires the software to be aware of which specific pages must be flushed and invalidated. The L2 cache in the AMD-K6-2E+ processor can be completely disabled by setting the L2 Disable (L2D) bit (EFER[4]) to 1 (see "Extended Feature Enable Register (EFER)" on page 47). If disabled in this manner, the processor does not access the L2 cache for any purpose, including allocations, read hits, write hits, snoops, inquire cycles, flushing, and read/write attempts by means of the L2AAR. (See "L2 Cache Testing" on page 213.) The L1 cache operation is not affected by disabling the L2 cache. The L2D bit is provided for debug and testing purposes only. For normal operation and maximum performance, this bit must be set to 0, which is the default setting following reset. The AMD-K6-2E+ processor does not provide a method for disabling the L1 cache while the L2 cache remains enabled. 212 Cache Organization Chapter 9