AMD AMD-K6-2/400 User Guide - Page 221

23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 8 Power-on Configuration and Initialization 8.1 FLUSH# BF[2:0] On power-on the system logic must reset the AMD-K6-2E+ processor by asserting the RESET signal. When the processor samples RESET asserted, it immediately flushes and initializes all internal resources and its internal state, including its pipelines and caches, the floating-point state, the MMX and 3DNow! states, and all registers. Then the processor jumps to address FFFF_FFF0h to start instruction execution. Signals Sampled During the Falling Transition of RESET FLUSH# is sampled on the falling transition of RESET to determine if the processor begins normal instruction execution or enters Three-State Test mode. s If FLUSH# is High during the falling transition of RESET, the processor unconditionally runs its Built-In Self Test (BIST), performs the normal reset functions, then jumps to address FFFF_FFF0h to start instruction execution. (See "Built-In Self-Test (BIST)" on page 251 for more details.) s If FLUSH# is Low during the falling transition of RESET, the processor enters Three-State Test mode. (See "Three-State Test Mode" on page 252 and "FLUSH# (Cache Flush)" on page 112 for more details.) The internal operating frequency of the processor is determined by the state of the bus frequency signals BF[2:0] when they are sampled during the falling transition of RESET. The frequency of the CLK input signal is multiplied internally by a ratio defined by BF[2:0]. (See "BF[2:0] (Bus Frequency)" on page 101 for the processor-clock to bus-clock ratios.) Chapter 8 Power-on Configuration and Initialization 199