AMD AMD-K6-2/400 User Guide - Page 136

Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 5.26 HLDA (Hold Acknowledge) Pin Attribute Summary Output When HOLD is sampled asserted, the processor completes the current bus cycles, floats the processor bus, and asserts HLDA in an acknowledgment that these events have been completed. The processor does not assert HLDA until the completion of a locked sequence of cycles. While HLDA is asserted, another bus master can drive cycles on the bus, including inquire cycles to the processor. The following signals are floated when HLDA is asserted: A[31:3], ADS #, ADSC #, AP, BE[7:0]#, CACHE #, D[63:0], D/C#, DP[7:0], LOCK #, M/IO#, PCD, PWT, SCYC, and W/R #. The processor is designed so that HLDA does not glitch. Driven HLDA is always driven except in the Three-State Test mode. If a processor cycle is in progress while HOLD is sampled asserted, HLDA is asserted one clock edge after the last BRDY # of the cycle is sampled asserted. If the bus is idle, HLDA is asserted one clock edge after HOLD is sampled asserted. HLDA is negated one clock edge after the clock edge on which HOLD is sampled negated. The assertion of HLDA is independent of the sampled state of BOFF #. The processor floats the bus every clock in which HLDA is asserted. 114 Signal Descriptions Chapter 5