AMD AMD-K6-2/400 User Guide - Page 233

23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Table 38. CACHE# Signal Generation Cycle Type CI Bit of TR12 PCD Signal Access Within WC/UC Range1 Writebacks X X X Unlocked Reads 0 0 0 Locked Reads X X X Single Writes X X X Any Cycle Except Writebacks 1 X X Any Cycle Except Writebacks X 1 X Any Cycle Except Writebacks X X 1 Notes: 1. WC and UC refer to Write-Combining and Uncacheable Memory Ranges as defined in the UWCCR. CACHE# Low Low High High High High High Cache-Related Signals Complete descriptions of the signals that control cacheability and cache coherency are given on the following pages: s CACHE#-page 105 s EADS#-page 109 s FLUSH#-page 112 s HIT#-page 113 s HITM#-page 113 s INV-page 118 s KEN#-page 119 s PCD-page 124 s PWT-page 126 s WB/WT#-page 139 9.4 Cache Disabling and Flushing L1 and L2 Cache Disabling To completely disable all accesses to the L1 and the L2 caches, the CD bit must be set to 1 and the caches must be completely flushed. There are three different methods for flushing the caches. The first method relies on the system logic and the other two methods rely on software. s For the system logic to flush the caches, the processor must sample FLUSH# asserted. In this method, the processor writes back any L1 data cache and L2 cache lines that are in Chapter 9 Cache Organization 211