AMD AMD-K6-2/400 User Guide - Page 225
State of Processor After INIT, The recognition of the assertion of INIT causes the processor
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23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 8.4 State of Processor After INIT The recognition of the assertion of INIT causes the processor to empty its pipelines, to initialize most of its internal state, and to branch to address FFFF_FFF0h-the same instruction execution starting point used after RESET. Unlike RESET, the processor preserves the contents of its caches, the floating-point state, the MMX and 3DNow! states, MSRs, and the CD and NW bits of the CR0 register. The edge-sensitive interrupts FLUSH# and SMI# are sampled and preserved during the INIT process and are handled accordingly after the initialization is complete. However, the processor resets any pending NMI interrupt upon sampling INIT asserted. INIT can be used as an accelerator for 80286 code that requires a reset to exit from Protected mode back to Real mode. Chapter 8 Power-on Configuration and Initialization 203