AMD AMD-K6-2/400 User Guide - Page 247
Table 40., Valid L1 and L2 Cache States and Effect of Inquire Cycles
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23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Table 40 shows all possible cache-line states before and after inquire cycles. Table 40. Valid L1 and L2 Cache States and Effect of Inquire Cycles Cache State Before Inquire1 Memory Access2 Cache State After Inquire INV = 0 INV = 1 L1 L2 I M Writeback L2 to bus I E - I S - I I - E3 M3 Writeback L2 to bus E E - E I - M E Writeback L1 to bus M I Writeback L1 to bus S S - S I - L1 L2 L1 L2 I S I I I S I I I S I I I I I I S S I I S S I I S I I I S I I I S I I I S S I I S I I I Notes: 1. M = Modified, E = Exclusive, S = Shared, I = Invalid. The exclusive and shared states are indistinguishable in the L1 instruction cache and are treated as "valid" states. 2. Writeback cycles to the bus are 32-byte burst writes. 3. This entry only applies to the L1 instruction cache. By design, a cache line cannot exist in the exclusive state in the L1 data cache and in the modified state in the L2 cache. Chapter 9 Cache Organization 225