AMD AMD-K6-2/400 User Guide - Page 224
Table 35., Register State After RESET continued, Power-on Configuration and Initialization,
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Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Table 35. Register State After RESET (continued) Register DR2 DR1 DR0 MCAR3 MCTR3 TR123 TSC3 EFER3 STAR3 WHCR3 UWCCR3 PSOR5 PFIR3,5 EPMR3,6 State (hex) 0000_0000h 0000_0000h 0000_0000h 0000_0000_0000_0000h 0000_0000_0000_0000h 0000_0000_0000_0000h 0000_0000_0000_0000h 0000_0000_0000_0002h 0000_0000_0000_0000h 0000_0000_0000_0000h 0000_0000_0000_0000h 0000_0000_0000_01SBh 0000_0000_0000_0000h 0000_0000_0000_0000h Notes: 1. The contents of EAX indicate if BIST was successful. If EAX = 0000_0000h, BIST was successful. If EAX is non-zero, BIST failed. 2. EDX contains the AMD-K6-2E+ processor signature, where X indicates the processor Stepping ID. 3. The contents of these registers are preserved following the recognition of INIT. 4. The CD and NW bits of CR0 are preserved following the recognition of INIT. 5. "S" represents the Stepping. "B" represents PSOR[3:0], where PSOR[3] equals 0, and PSOR[2:0] is equal to the value of the BF[2:0] signals sampled during the falling transition of RESET. 6. Supported on low-power versions only. 202 Power-on Configuration and Initialization Chapter 8