AMD AMD-K6-2/400 User Guide - Page 8

Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 13.4 Cache Inhibit 263 13.5 L2 Cache and Tag Array Testing 264 13.6 Debug 268 14 Clock Control 275 14.1 Clock Control States 275 14.2 Halt State 278 14.3 Stop Grant State 278 14.4 Stop Grant Inquire State 280 14.5 EPM Stop Grant State 281 14.6 Stop Clock State 283 15 Electrical Data 285 15.1 Operating Ranges 286 15.2 Absolute Ratings 287 15.3 DC Characteristics 287 15.4 Power Dissipation 289 15.5 Power and Grounding 291 16 Signal Switching Characteristics 295 16.1 CLK Switching Characteristics 296 16.2 Clock Switching Characteristics for 100-MHz Bus Operation 296 16.3 Clock Switching Characteristics for 66-MHz Bus Operation 297 16.4 Valid Delay, Float, Setup, and Hold Timings 298 16.5 Output Delay Timings for 100-MHz Bus Operation 298 16.6 Input Setup and Hold Timings for 100-MHz Bus Operation 300 16.7 Output Delay Timings for 66-MHz Bus Operation 302 16.8 Input Setup and Hold Timings for 66-MHz Bus Operation 304 16.9 RESET and Test Signal Timing 306 16.10 Timing Diagrams 309 17 Thermal Design 313 17.1 Package Thermal Specifications 313 17.2 Measuring Case Temperature 317 17.3 Layout and Airflow Considerations 317 18 Pin Designations 321 18.1 Pins Designations for CPGA Package 322 18.2 Pins Designations for OBGA Package 326 19 Package Specifications 331 19.1 321-Pin Staggered CPGA Package Specification 331 19.2 349-Ball OBGA Package Specification 332 20 Ordering Information 333 Index 335 viii Contents