AMD AMD-K6-2/400 User Guide - Page 40

Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 (two bytes) organization. Therefore, instructions are loaded and replaced with word granularity. When a control transfer occurs - such as a JMP instruction - the entire instruction buffer is flushed and reloaded with a new set of 16 instruction bytes. 32-Kbyte Level-One Instruction Cache 16 Bytes 16 Bytes Branch-Target Cache 16 x 16 Bytes Branch Target Address Adders Return Address Stack 16 x 16 Bytes 2:1 Fetch Unit 16 Instruction Bytes plus 16 Sets of Predecode Bits Instruction Buffer Figure 3. The Instruction Buffer Instruction Decode The AMD-K6-2E+ processor decode logic is designed to decode multiple x86 instructions per clock (see Figure 4 on page 19). The decode logic accepts x86 instruction bytes and their predecode bits from the instruction buffer, locates the actual instruction boundaries, and generates RISC86 operations from these x86 instructions. RISC86 operations are fixed-length internal instructions. Most RISC86 operations execute in a single clock. RISC86 operations are combined to perform every function of the x86 instruction set. Some x86 instructions are decoded into as few as zero RISC86 operations - for instance a NOP - or one RISC86 18 Internal Architecture Chapter 2