AMD AMD-K6-2/400 User Guide - Page 253

23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 10.2 Table 42 summarizes the three settings of the EWBEC field for the EFER register, along with the effect of write ordering and performance. For more information on the EFER register, see "Extended Feature Enable Register (EFER)" on page 47. Table 42. EWBEC Settings and Performance EFER[3] EFER[2] Write (GEWBED) (SEWBED) Ordering 1 0 or 1 None 0 1 All except UC/WC 0 0 All Performance Best Close-to-Best Slowest Memory Type Range Registers The AMD-K6-2E+ processor provides two variable-range Memory Type Range Registers (MTRRs)-MTRR0 and MTRR1-that each specify a range of memory. Each range can be defined as one of the following memory types: s Uncacheable (UC) Memory-Memory read cycles are sourced directly from the specified memory address and the processor does not allocate a cache line. Memory write cycles are targeted at the specified memory address and a write allocation does not occur. s Write-Combining (WC) Memory-Memory read cycles are sourced directly from the specified memory address and the processor does not allocate a cache line. The processor conditionally combines data from multiple noncacheable write cycles that are addressed within this range into a merge buffer. Merging multiple write cycles into a single write cycle reduces processor bus utilization and processor stalls, thereby increasing the overall system performance. This memory type is applicable for linear video frame buffers. Chapter 10 Write Merge Buffer 231