AMD AMD-K6-2/400 User Guide - Page 44
Execution Units, units-store, load, integer X ALU, MMX ALU - + multiplier
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Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 RISC86 #0 From Decode Logic RISC86 #1 RISC86 #2 RISC86 #3 Centralized RISC86® Operation Scheduler RISC86 Issue Buses RISC86 Operation Buffer Figure 5. AMD-K6™-2E+ Processor Scheduler 2.5 Execution Units The AMD-K6-2E+ processor contains ten parallel execution units-store, load, integer X ALU, integer Y ALU, MMX ALU (X), MMX ALU (Y), MMX/3DNow! multiplier, 3DNow! ALU, floating-point, and branch condition. Each unit is independent and capable of handling the RISC86 operations issued to it. Table 1 on page 23 details the execution units, functions performed within these units, operation latency, and operation throughput. Note that the integer, MMX, and 3DNow! execution units share the register X and Y issue pipelines. See "Register X and Y Pipelines" on page 24. The store and load execution units are two-stage pipelined designs. s The store unit performs data writes and register calculation for LEA/PUSH instructions. Data memory and register 22 Internal Architecture Chapter 2