AMD AMD-K6-2/400 User Guide - Page 365

23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet HITM 113 HLDA 114 HOLD 115 IGNNE 116, 240 INIT 117, 278, 281 INTR 118, 278, 281 INV 118 KEN 119 LOCK 120 logic symbol (figure 91 M/IO 121 NA 122 negated 93 NMI 123, 278, 281 output 200 PCD 124 PCHK 125 PWT 126 RESET 127, 278, 281 RSVD 128 sampled 93 sampled during RESET 199 SCYC 129 SMI 130, 241, 278, 281 SMIACT 131, 241 STPCLK 132, 278 switching characteristics 295 TCK 133 TDI 133 TDO 133 terminology 93 Test Access Port (TAP 254 timing (figures 159-197, 309-312 TMS 134 TRST 134 VCC2DET 135 VCC2H/L 136 VID[4:0 137, 151 W/R 138 WB/WT 139 SIMD 15 Single Instruction Multiple Data (SIMD) operations . . . . . 15 Single-Transfer Memory Read and Write 158 SMI# Signal 130, 241, 278 SMIACT# Signal 131, 241 SMM 241 Snooping 131, 139, 164 cache states (table 226 data cache 223 instruction cache 223 internal cache 223 processor-initiated 223 Software Environment 27 descriptors 59 exceptions (table 62 gates 59 instructions supported 63 interrupts (table 62 memory management registers 54 model-specific registers (MSR 44 paging 56 registers 27 Software Prefetching 220 Special Bus Cycles BRDY# timing 103 cache invalidation 190 Index cache writeback invalidation 190 definition (table 142 differentiating 142, 190 encoding 142, 190 enhanced power management 145 EPM stop grant 190 EWBE# timing 110 examples 190 flush acknowledge 112, 164, 190, 212 halt 190-191, 278 shutdown 190, 192 signal states (table 142 stop grant 132, 190, 193, 279 System Management Mode (SMM 247 Speculative EWBE# Disable (SEWBED 230 Split Cycle 129 Standard-Power Devices 4, 286, 334 STAR 44, 48, 202 State bus machine (figure 155 cache 221 processor after INIT 203 after RESET 200 Stepping ID 202 Stop clock 132 power dissipation 289-290 clock state 193, 283 grant inquire state 275, 278-280 state 193, 278, 280 grant state 281 Stop Grant Time-Out Counter Field 150 Storage Temperature 287 STPCLK# Signal 132, 278 Super7 Platform 1 advantages 9 initiative 8 Switching Characteristics 296 100-MHz bus operation 296 66-MHz bus operation 297 input setup and hold timings for 100-MHz bus 300 input setup and hold timings for 66-MHz bus 304 output delay timings for 100-MHz bus 298 output delay timings for 66-MHz bus 302 signal 295 valid delay, float, setup, and hold timings 298 SYSCALL Instruction 80 SYSCALL/SYSRET Target Address Register (STAR) . 44, 48, 202 SYSRET Instruction 80 System management interrupt 130 management interrupt active 131 System Design airflow management 319 ATX form factor 320 component placement 292 decoupling recommendations 292 heatsink 318 pin connection requirements 293 power connections 291 voltage regulator 317 343