AMD AMD-K6-2/400 User Guide - Page 239
Write Handling Control Register WHCR, Write Allocate Enable Limit Field.
View all AMD AMD-K6-2/400 manuals
Add to My Manuals
Save this manual to your list of manuals |
Page 239 highlights
23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 63 32 31 22 21 17 16 15 0 W A WAELIM E 1 5 M Reserved Symbol WAELIM WAE15M Description Bits Write Allocate Enable Limit 31-22 Write Allocate Enable 15-to-16-Mbyte 16 Notes: Hardware RESET initializes this MSR to all zeros. Figure 84. Write Handling Control Register (WHCR) Write Allocate Enable Limit Field. The WAELIM field is 10 bits wide. This field, multiplied by 4 Mbytes, defines an upper memory limit. Any pending write cycle that misses the L1 cache and that addresses memory below this limit causes the processor to perform a write allocate (assuming the address is not within a range where write allocates are disallowed). Write allocate is disabled for memory accesses at and above this limit unless the processor determines a pending write cycle is cacheable by means of one of the other write allocate mechanisms-"Write to a Cacheable Page" and "Write to a Sector." The maximum value of this limit is ((210-1) · 4 Mbytes) = 4092 Mbytes. When all the bits in this field are set to 0, all memory is above this limit and write allocates due to this mechanism is disabled (even if all bits in the WAELIM field are set to 0, write allocates can still occur due to the "Write to a Cacheable Page" and "Write to a Sector" mechanisms). Write Allocate Enable 15-to-16-Mbyte Bit. The Write Allocate Enable 1 5-t o -1 6 -M by t e ( WA E1 5 M) b it i s u se d t o e n able w r it e allocations for memory write cycles that address the 1 Mbyte of memory between 15 Mbytes and 16 Mbytes. This bit must be set to 1 to allow write allocate in this memory area. This bit is provided to account for a small number of uncommon memory-mapped I/O adapters that use this particular memory address space. If the system contains one of these peripherals, the bit should be set to 0 (even if the WAE15M bit is set to 0, write allocates can still occur between 15 Mbytes and 16 Mbytes due to the "Write to a Cacheable Page" and "Write to a Chapter 9 Cache Organization 217