AMD AMD-K6-2/400 User Guide - Page 362

Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 states (table 221, 225-226 write allocate 215 L2 Cache 112-113, 139, 142 access type 265 built-in self test 251 cache line (figure 207 cache sector and line organization (figure 265 cache-line fills 214 cache-line replacements 214 coherency 222 data location (figure 51 data reads 266 direct access 50 disabling 211-212 disabling for debug 47 flushing 223 inquire cycles (table 225 least recently used (LRU) algorithm 215 Level-2 Cache Array Access Register (L2AAR 50 LRU field 267 MESI states 207 operation 209 organization 205 organization (figure 206, 265 predecode bits not stored 208 prefetching 220 sector organization (figure 16 states (table 221, 225-226 Super7 platform support 8 T/D bit 265 tag array testing 213, 264 tag information (figure 52 tag location (figure 51 testing 264 write allocate 215 L2AAR 44, 50, 212-213, 264-266 L3 Cache debugging 263 PCD signal 264 testing 263 Latency, execution (table 23 Layout and Airflow Considerations 317 Level-2 Cache Array Access Register (L2AAR). . . . . 264-266 Literature iii LOCK# Signal 120 Locked cycles 184 operation with BOFF# intervention 186 operation, basic 184 Logic branch-prediction 15, 23, 25-26 external support of floating-point exceptions 238 symbol (figure 91 Low-Power Devices 4, 286, 289, 334 M M/IO# Signal 121 Machine Check Address Register (MCAR 44-45, 202 Machine Check Exception 45 Machine Check Type Register (MCTR 44-45, 202 Maskable Interrupt 118 MCAR 44-45, 202 MCTR 44-45, 202 Memory management registers 54 or I/O 121 read and write, misaligned single-transfer 160 read and write, single-transfer 158 reads and writes 158 type range registers (MTRR 49, 231 MESI 1, 168, 172, 206, 227 bit 16, 207, 209 states in the data cache 207 Microarchitecture 3, 11-26 branch-prediction 25 cache 16 centralized scheduler 21 decoders 13 enhanced RISC86 12 execution units 22 instruction fetching and decode 17 instruction prefetch 16 overview 11 predecode 16 Misaligned I/O read and write 167 I/O transfers (table 167 memory transfers (table 160 single-transfer memory read and write 160 transfers 129 MMX Technology 19, 21-24, 127 3DNow!™ registers 35 data types 37 exceptions 240 INIT state 203 instruction compatibility, floating-point and 240 instructions 240 instructions (table 86 register operation 14 registers 35 RESET state 199 Model-Specific Registers (MSR 44 MSR 44 MTRR 49, 231 Multimedia and 3DNow!™ execution units 239 execution unit 24, 239 functional unit 23 N NA# Signal 122 Negated signal 93 Next Address 122 NMI Signal 123, 242, 278 No-Connect Pins 128, 293 Non-Maskable Interrupt 123 Non-Pipelined Single-Transfer Memory Read/Write and Write Delayed by EWBE 159 Normal State 275 O OBGA Package 2-3 pin designations (figure 326 pin designations by function (table 328 pin differences (table 321 specification 332 340 Index