AMD AMD-K6-2/400 User Guide - Page 170

Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Processor State Observability Register (PSOR) To support AMD PowerNow! technology, all low-power versions of the AMD-K6-2E+ processor provide a different version of the Processor State Observability Register (PSOR), as shown in Figure 57 and fully described in this section. All standardpower versions of the processor support the PSOR register as defined on page 49. The PSOR register is MSR C000_0087h. . Symbol PBF VID Description Pin Bus Frequency Divisor Voltage ID Bits 23-21 20-16 63 24 23 21 20 16 15 98 7 4 32 0 PBF[2:0] VID N O STEP L 2 EBF[2:0] Symbol NOL2 STEP EBF Reserved Description Bits No L2 Functionality 8 Processor Stepping 7-4 Effective Bus Frequency Divisor 2-0 Figure 57. Processor State Observability Register (PSOR)-Low-Power Versions of the Processor PBF[2:0] Field. This read-only field contains the BF divisor values externally applied to the processor BF[2:0] pins. These input BF values are sampled by the processor during the falling transition of RESET. Note: This BF divisor value may be different than the BF divisor value supplied to the processor's internal PLL. VID Field. This read-only field contains the Voltage ID bits driven to the processor VID[4:0] pins at RESET. These bits are initialized to 01010b and driven on the VID[4:0] pins at RESET. Note: Low-power AMD-K6-2E+ processors support AMD PowerNow! technology, which enables dynamic alteration of the processor's core voltage. See "Enhanced Power Management Register (EPMR)" on page 144 for information on programming the VID[4:0] pins. NOL2 Bit. This read-only bit indicates whether the processor contains an L2 cache. This bit is always set to 0 for the AMD-K6-2E+ processor. 148 AMD PowerNow!™ Technology Chapter 6