AMD AMD-K6-2/400 User Guide - Page 229

23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet L1 Instruction Cache Line Tag Cache Line 0 Byte 31 Predecode Bits Byte 30 Predecode Bits Byte 0 Predecode Bits 1 MESI Bit Address Cache Line 1 Byte 31 Predecode Bits Byte 30 Predecode Bits Byte 0 Predecode Bits 1 MESI Bit L1 Data Cache Line and L2 Cache Line Tag Cache Line 0 Byte 31 Address Cache Line 1 Byte 31 Byte 30 Byte 30 Byte 0 2 MESI Bits Byte 0 2 MESI Bits Note: L1 instruction-cache lines have only two coherency states (valid or invalid) rather than the four MESI coherency states of L1 data-cache and L2 cache lines. Only two states are needed for the L1 instruction cache because these lines are read-only. Figure 83. L1 Cache Sector Organization 9.1 MESI States in the L1 Data Cache and L2 Cache The state of each line in the caches is tracked by the MESI bits. The coherency of these states or MESI bits is maintained by internal processor snoops and external inquire cycles by the system logic. The following four states are defined for the L1 data cache and the L2 cache: s Modified-This line has been modified and is different from external memory. s Exclusive-In general, an exclusive line in the L1 data cache or the L2 cache is not modified and is the same as external memory. The exception is the case where a line exists in the modified state in the L1 data cache and also resides in the L2 cache. By design, the line in the L2 cache must be in the exclusive state. s Shared-If a cache line is in the shared state it means that the same line can exist in more than one cache system. s Invalid-The information in this line is not valid. Chapter 9 Cache Organization 207