AMD AMD-K6-2/400 User Guide - Page 172

Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 6.2 Dynamic Core Frequency and Core Voltage Control AMD PowerNow! technology-enabled processors support the ability to change the bus frequency divisor and core voltage transparently to the user during run-time. These features are implemented in conjunction with a new clock control state- the EPM Stop Grant state. For AMD PowerNow! technology state transitions, the EPMR register is accessed using an SMM handler. s The SMM handler initiates core voltage and frequency transitions by writing a non-zero value to the Stop Grant Time-Out Counter (SGTC) field. s This action automatically places the processor into the EPM Stop Grant State and transitions the CPU core voltage and frequency to the values specified in the Voltage ID Output (VIDO) and Internal BF Divisor (IBF) fields of the BVC field. s Once the timer of the SGTC has expired, the EPM Stop Grant State is exited and the AMD PowerNow! technology state transition is completed. Effective Bus Frequency Divisor (EBF[2:0]) See "Clock Control" on page 275 for more information about the EPM Stop Grant State. The processor core frequency is controlled by the Effective Bus Frequency Divisor-EBF[2:0]-which dictates the processor-tobus clock ratio supplied to the processor's internal PLL. This processor-to-bus clock ratio is multiplied by the external bus frequency to set the frequency of operation for the processor core. s At the fall of RESET, the EBF[2:0] value is determined by the state of the processor BF[2:0] input pins. s Afterwards, the EBF[2:0] value can be dynamically controlled through AMD PowerNow! technology state transitions. Table 28 on page 149 lists valid EBF[2:0] states and equivalent processor-to-bus clock ratios. 150 AMD PowerNow!™ Technology Chapter 6