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23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 AN AM INC INC VCC2H/L# FLUSH# Vcc2 Vcc2 Vcc2 Vcc2 Vcc2 Vcc2 Vcc3 Vcc3 Vcc3 Vcc3 Vcc3 A10 A6 VID1 Vss ADSC# EADS# W/R# Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss A8 A4 A30 AN AM AL VCC2DET PWT HITM# INC BE0# BE2# BE4# BE6# SCYC NC A20 A18 A16 A14 A12 A11 A7 A3 Vss AK AP D/C# HIT# A20M# BE1# BE3# BE5# BE7# CLK RESET A19 A17 A15 A13 A9 A5 A29 A28 AL AK AJ AH AG BREQ HLDA ADS# Vss Vss Vcc2 Vss NC Vss Vcc3 Vss NC Vss Vss Vcc3 Vss A31 A25 Vss Vss LOCK# VID0 A26 A22 AF Vcc2 SMIACT# PCD A27 A24 Vcc3 AE Vss PCHK# A21 Vss AD AC Vcc2 RSVD APCHK# Vss RSVD AB Vcc2 RSVD RSVD AA Vss HOLD A23 RSVD Vcc3 INTR Vss NMI INC Vcc3 SMI# Vss Z Vcc2 RSVD WB/WT# INIT IGNNE# Vcc3 Y Vss BOFF# INC Vss X W Vcc2 BRDYC# NA# Vss BRDY# BF0 INC Vcc3 BF1 Vss V U Vcc2 EWBE# KEN# Vss AHOLD Bottom NC BF2 Vcc3 STPCLK# Vss AJ AH AG AF AE AD AC AB AA Z Y X W V U T Vcc2 CACHE# INV S Vss M/IO# R Vcc2 RSVD RSVD Q Vss RSVD View Vcc3 Vss Vcc3 Vcc3 Vss NC NC Vcc3 VID2 Vss T S R Q P Vcc2 RSVD FERR# N Vss RSVD TRST# RSVD Vcc3 P TMS Vss N M Vcc2 D63 DP7 TDO TDI Vcc3 L Vss D62 TCK Vss K Vcc2 D61 D60 Vcc3 RSVD Vcc3 Vss D59 J Vcc2 D57 D58 H Vss D56 D0 Vss RSVD D2 Vcc3 INC Vss G F E D Vcc2 D55 D53 D3 D1 Vcc3 DP6 D51 DP5 D5 D4 D54 D52 D49 D46 D42 Vss Vss Vcc2 VID4 Vss Vcc3 Vss VID3 Vcc3 Vss Vss D7 D6 Vcc3 D48 D44 D40 D39 D37 D35 D33 DP3 D30 D28 D26 D23 D19 DP1 D12 D8 DP0 C NC D47 D45 DP4 D38 D36 D34 D32 D31 D29 D27 D25 DP2 D24 D21 D17 D14 D10 D9 M L K J H G F E D C B Vcc2 D43 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss D20 D16 D13 D11 B A Vss D41 Vcc2 Vcc2 Vcc2 Vcc2 Vcc2 Vcc2 Vcc3 Vcc3 Vcc3 Vcc3 Vcc3 Vcc3 D22 D18 D15 NC A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Notes: The VID[4:0] outputs are supported on low-power versions only. These pins are defined as no-connects on standard-power versions. Figure 122. CPGA Connection Diagram (Bottom-Side View) Chapter 18 Pin Designations 323

Section	Page
IF YOU HAVE QUESTIONS, WE\	3
Contents	5
List of Figures	9
List of Tables	13
Revision History	17
About this Data Sheet	19
1 AMDK6™2E+ Embedded Processor	23
1.1 AMDK6™2E+ Embedded Processor Features	25
1.2 Process Technology	29
1.3 Super7™ Platform	30
2 Internal Architecture	33
2.1 Microarchitecture Overview	33
2.2 Cache, Instruction Prefetch, and Predecode Bits	38
2.3 Instruction Fetch and Decode	39
2.4 Centralized Scheduler	43
2.5 Execution Units	44
2.6 BranchPrediction Logic	47
3 Software Environment	49
3.1 Registers	49
3.2 ModelSpecific Registers (MSR)	66
3.3 Memory Management Registers	76
3.4 Paging	78
3.5 Descriptors and Gates	81
3.6 Exceptions and Interrupts	84
3.7 Instructions Supported by the AMDK6™2E+ Processor	85
4 Logic Symbol Diagram	113
5 Signal Descriptions	115
5.1 Signal Terminology	115
5.2 A20M# (Address Bit 20 Mask)	116
5.3 A[31:3] (Address Bus)	117
5.4 ADS# (Address Strobe)	118
5.5 ADSC# (Address Strobe Copy)	118
5.6 AHOLD (Address Hold)	119
5.7 AP (Address Parity)	120
5.8 APCHK# (Address Parity Check)	121
5.9 BE[7:0]# (Byte Enables)	122
5.10 BF[2:0] (Bus Frequency)	123
5.11 BOFF# (Backoff)	124
5.12 BRDY# (Burst Ready)	125
5.13 BRDYC# (Burst Ready Copy)	126
5.14 BREQ (Bus Request)	126
5.15 CACHE# (Cacheable Access)	127
5.16 CLK (Clock)	127
5.17 D/C# (Data/Code)	128
5.18 D[63:0] (Data Bus)	129
5.19 DP[7:0] (Data Parity)	130
5.20 EADS# (External Address Strobe)	131
5.21 EWBE# (External Write Buffer Empty)	132
5.22 FERR# (FloatingPoint Error)	133
5.23 FLUSH# (Cache Flush)	134
5.24 HIT# (Inquire Cycle Hit)	135
5.25 HITM# (Inquire Cycle Hit To Modified Line)	135
5.26 HLDA (Hold Acknowledge)	136
5.27 HOLD (Bus Hold Request)	137
5.28 IGNNE# (Ignore Numeric Exception)	138
5.29 INIT (Initialization)	139
5.30 INTR (Maskable Interrupt)	140
5.31 INV (Invalidation Request)	140
5.32 KEN# (Cache Enable)	141
5.33 LOCK# (Bus Lock)	142
5.34 M/IO# (Memory or I/O)	143
5.35 NA# (Next Address)	144
5.36 NMI (NonMaskable Interrupt)	145
5.37 PCD (Page Cache Disable)	146
5.38 PCHK# (Parity Check)	147
5.39 PWT (Page Writethrough)	148
5.40 RESET (Reset)	149
5.41 RSVD (Reserved)	150
5.42 SCYC (Split Cycle)	151
5.43 SMI# (System Management Interrupt)	152
5.44 SMIACT# (System Management Interrupt Active)	153
5.45 STPCLK# (Stop Clock)	154
5.46 TCK (Test Clock)	155
5.47 TDI (Test Data Input)	155
5.48 TDO (Test Data Output)	155
5.49 TMS (Test Mode Select)	156
5.50 TRST# (Test Reset)	156
5.51 VCC2DET (VCC2 Detect)	157
5.52 VCC2H/L# (VCC2 High/Low)	158
5.53 VID[4:0] (Voltage Identification)	159
5.54 W/R# (Write/Read)	160
5.55 WB/WT# (Writeback or Writethrough)	161
5.56 Pin Tables by Type	162
5.57 Bus Cycle Definitions	164
6 AMD PowerNow!™ Technology	165
6.1 Enhanced Power Management Features	165
6.2 Dynamic Core Frequency and Core Voltage Control	172
7 Bus Cycles	175
7.1 Timing Diagrams	175
7.2 Bus States	177
7.3 Memory Reads and Writes	180
7.4 I/O Read and Write	188
7.5 Inquire and Bus Arbitration Cycles	190
7.6 Special Bus Cycles	212
8 Poweron Configuration and Initialization	221
8.1 Signals Sampled During the Falling Transition of RESET	221
8.2 RESET Requirements	222
8.3 State of Processor After RESET	222
8.4 State of Processor After INIT	225
9 Cache Organization	227
9.1 MESI States in the L1 Data Cache and L2 Cache	229
9.2 Predecode Bits	230
9.3 Cache Operation	230
9.4 Cache Disabling and Flushing	233
9.5 L2 Cache Testing	235
9.6 CacheLine Fills	235
9.7 CacheLine Replacements	236
9.8 Write Allocate	237
9.9 Prefetching	242
9.10 Cache States	243
9.11 Cache Coherency	244
9.12 Writethrough and Writeback Coherency States	249
9.13 A20M# Masking of Cache Accesses	249
10 Write Merge Buffer	251
10.1 EWBE# Control	251
10.2 Memory Type Range Registers	253
10.3 Memory-Range Restrictions	255
10.4 Examples	257
11 FloatingPoint and Multimedia Execution Units	259
11.1 FloatingPoint Execution Unit	259
11.2 Multimedia and 3DNow!™ Execution Units	261
11.3 FloatingPoint and MMX™/3DNow!™ Instruction Compatibility	262
12 System Management Mode (SMM)	263
12.1 SMM Operating Mode and Default Register Values	263
12.2 SMM StateSave Area	265
12.3 SMM Revision Identifier	267
12.4 SMM Base Address	268
12.5 Halt Restart Slot	268
12.6 I/O Trap Doubleword	269
12.7 I/O Trap Restart Slot	270
12.8 Exceptions, Interrupts, and Debug in SMM	272
13 Test and Debug	273
13.1 BuiltIn SelfTest (BIST)	273
13.2 ThreeState Test Mode	274
13.3 BoundaryScan Test Access Port (TAP)	275
13.4 Cache Inhibit	285
13.5 L2 Cache and Tag Array Testing	286
13.6 Debug	290
14 Clock Control	297
14.1 Clock Control States	297
14.2 Halt State	300
14.3 Stop Grant State	300
14.4 Stop Grant Inquire State	302
14.5 EPM Stop Grant State	303
14.6 Stop Clock State	305
15 Electrical Data	307
15.1 Operating Ranges	308
15.2 Absolute Ratings	309
15.3 DC Characteristics	309
15.4 Power Dissipation	311
15.5 Power and Grounding	313
16 Signal Switching Characteristics	317
16.1 CLK Switching Characteristics	318
16.2 Clock Switching Characteristics for 100MHz Bus Operation	318
16.3 Clock Switching Characteristics for 66MHz Bus Operation	319
16.4 Valid Delay, Float, Setup, and Hold Timings	320
16.5 Output Delay Timings for 100MHz Bus Operation	320
16.6 Input Setup and Hold Timings for 100MHz Bus Operation	322
16.7 Output Delay Timings for 66MHz Bus Operation	324
16.8 Input Setup and Hold Timings for 66MHz Bus Operation	326
16.9 RESET and Test Signal Timing	328
16.10 Timing Diagrams	331
17 Thermal Design	335
17.1 Package Thermal Specifications	335
17.2 Measuring Case Temperature	339
17.3 Layout and Airflow Considerations	339
18 Pin Designations	343
18.1 Pins Designations for CPGA Package	344
18.2 Pins Designations for OBGA Package	348
19 Package Specifications	353
19.1 321Pin Staggered CPGA Package Specification	353
19.2 349Ball OBGA Package Specification	354
20 Ordering Information	355

Match case Limit results 1 per page

Chapter 18

Pin Designations

323

23542A/0—September 2000

AMD-K6™-2E+ Embedded Processor Data Sheet

Preliminary Information

Notes:

The VID[4:0] outputs are supported on low-power versions only. These pins are defined as no-connects on standard-power versions.

Figure 122.

CPGA Connection Diagram (Bottom-Side View)

Bottom

View

HOLD

HLDA

ADS#

BREQ

APCHK#

LOCK#

PCHK#

PCD

D/C#

PWT

BE1#

BE2#

BE3#

BE5#

BE0#

BE4#

BE6#

RSVD

BE7#

RSVD

ADSC#

EADS#

BRDY#

BRDYC#

BOFF#

EWBE#

RSVD

AHOLD

M/IO#

FERR#

WB/WT#

KEN#

SMIACT#

A20M#

RESET

A20

A19

A17

A18

A15

HITM#

VCC2DET

D63

DP7

D61

D57

D59

D58

D55

D53

D62

D60

D56

DP5

D51

DP6

D54

D44

D42

D39

D33

D52

D49

D40

D35

DP3

D37

D46

D47

D45

DP4

D48

D43

D41

D38

D36

D34

D32

D31

D27

D29

D25

DP2

D30

D28

D26

D23

RSVD

D19

DP1

D12

D24

D21

D17

DP0

D14

D11

D15

D10

D20

D22

D13

D16

D18

TDO

TDI

TCK

TMS

TRST#

BF0

BF1

BF2

STPCLK#

IGNNE#

INTR

SMI#

NMI

INIT

INC

A26

VID1

INC

VCC2H/L#

INC

FLUSH#

INC

A16

A30

A29

A28

A10

9 10 11 12 13 14

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

15 16

9 10 11 12 13 14

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

15 16

CACHE#

INV

NA#

SCYC

W/R#

A31

A25

A22

A24

A27

A23

A21

A12

A13

A14

A11

CLK

VID0

INC

HIT#

RSVD

VID2

VID3

VID4