AMD AMD-K6-2/400 User Guide - Page 254

Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 UC/WC Cacheability Control Register (UWCCR) . The MTRRs are accessed by addressing the 64-bit MSR known as the UC/WC Cacheability Control Register (UWCCR). The MSR address of the UWCCR is C000_0085h. Following reset, all bits in the UWCCR register are set to 0. MTRR0 (lower 32 bits of the UWCCR register) defines the size and memory type of range 0 and MTRR1 (upper 32 bits) defines the size and memory type of range 1 (see Figure 87). Symbol Description Bits UC1 Uncacheable Memory Type 32 WC1 Write-Combining Memory Type 33 Symbol Description Bits UC0 Uncacheable Memory Type 0 WC0 Write-Combining Memory Type 1 63 49 48 34 33 32 31 17 16 2 10 Physical Base Address 1 WU Physical Address Mask 1 C C 11 Physical Base Address 0 WU Physical Address Mask 0 C C 00 MTRR1 MTRR0 Figure 87. UC/WC Cacheability Control Register (UWCCR) Physical Base Address n (n=0, 1). T h i s a d d re s s i s t h e 1 5 m o s t significant bits of the physical base address of the memory range. The least-significant 17 bits of the base address are not needed because the base address is by definition always aligned on a 128-Kbyte boundary. Physical Address Mask n (n=0, 1). T h i s v a l u e i s t h e 1 5 m o s t significant bits of a physical address mask that is used to define the size of the memory range. This mask is logically ANDed with both the physical base address field of the UWCCR register and the physical address generated by the processor. If the results of the two AND operations are equal, then the generated physical address is considered within the range. That is, if: Mask & Physical Base Address = Mask & Physical Address Generated then, the physical address generated by the processor is in the range. 232 Write Merge Buffer Chapter 10