AMD AMD-K6-2/400 User Guide - Page 86

Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Opcode Bytes ModR/M Byte Decode Type RISC86® Operation s mmreg1-MMX/3DNow! register defined by bits 5, 4, and 3 of the modR/M byte s mmreg2-MMX/3DNow! register defined by bits 2, 1, and 0 of the modR/M byte s mreg16/32-word or doubleword integer register, or word or doubleword integer value in memory defined by the modR/M byte s mreg8-byte integer register or byte integer value in memory defined by the modR/M byte s reg8-byte integer register defined by instruction byte(s) or bits 5, 4, and 3 of the modR/M byte s reg16/32-word or doubleword integer register defined by instruction byte(s) or bits 5, 4, and 3 of the modR/M byte The second and third columns list all applicable opcode bytes. The fourth column lists the modR/M byte when used by the instruction. The modR/M byte defines the instruction as a register or memory form. If modR/M bits 7 and 6 are documented as mm (memory form), mm can only be 10b, 01b or 00b. The fifth column lists the type of instruction decode - short, long, and vector. The AMD-K6-2E+ processor decode logic can process two short, one long, or one vector decode per clock. The sixth column lists the type of RISC86 operation(s) required for the instruction. The operation types and corresponding execution units are as follows: s alu-either of the integer execution units s alux-integer X execution unit only s branch-branch condition unit s float-floating-point execution unit s limm-load immediate, instruction control unit s load, fload, mload-load unit s meu-multimedia execution units for MMX and 3DNow! instructions s store, fstore, mstore-store unit 64 Software Environment Chapter 3