AMD AMD-K6-2/400 User Guide - Page 299
Clock Control, Clock Control State Transitions for Low-Power Versions of
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23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet HLT Instruction RESET, SMI#, INIT, or INTR Asserted Normal Mode - Real - Virtual-8086 - Protected - SMM Non-zero value written to SGTC SGTC timer expires STPCLK# Asserted STPCLK# Negated, or RESET Asserted Halt State Stop Grant State EPM Stop Grant State EADS# Asserted CLK Stopped Writeback Completed CLK Started CLK Started CLK Stopped EADS# Asserted Writeback Completed Stop Grant Inquire State Stop Clock State Figure 102. Clock Control State Transitions for Low-Power Versions of the AMD-K6™-2E+ Processor Chapter 14 Clock Control 277
Chapter 14
Clock Control
277
23542A/0—September 2000
AMD-K6™-2E+ Embedded Processor Data Sheet
Preliminary Information
Figure 102.
Clock Control State Transitions for Low-Power Versions of the
AMD-K6™-2E+ Processor
CLK
Started
CLK
Stopped
SGTC timer expires
Non-zero value written to SGTC
EADS# Asserted
EADS# Asserted
HLT Instruction
Stop Grant
State
Normal Mode
– Real
– Virtual-8086
– Protected
– SMM
Halt
State
Stop Clock
State
RESET, SMI#, INIT,
or INTR Asserted
Stop Grant
Inquire
State
STPCLK# Asserted
STPCLK# Negated,
or RESET Asserted
CLK
Started
CLK
Stopped
Writeback
Completed
Writeback
Completed
EPM Stop Grant
State