AMD AMD-K6-2/400 User Guide - Page 288
L2 Cache Data Reads, L2 Tag or Data Location for the AMD-K6™-2E+ Processor-EDX
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Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 page 266 describes the operation that is performed based on the instruction and the T/D bit. Symbol Description T/D Selects Tag (1) or Data (0) access Way Selects desired cache way Bit 20 17-16 31 21 20 19 18 17 16 15 14 T / Way D Reserved Symbol Description Bit Set Selects the desired cache set 14-6 Line Selects Line1 (1) or Line0 (0) 5 Octet Selects one of four octets 4-3 Dword Selects upper (1) or lower (0) dword 2 6 5 4 32 1 0 L D Set i n e Octet w o r d Figure 93. L2 Tag or Data Location for the AMD-K6™-2E+ Processor-EDX L2 Cache Data Reads Table 53. Tag versus Data Selector Instruction T/D (EDX[20]) Operation RDMSR 0 Read dword from L2 data array into EAX. Dword location is specified by EDX. RDMSR 1 Read tag, line state and LRU information from L2 tag array into EAX. Location of tag is specified by EDX. WRMSR 0 Write dword to the L2 data array using data in EAX. Dword location is specified by EDX. WRMSR 1 Write tag, line state and LRU information into L2 tag array from EAX. Location of tag is specified by EDX. When the L2AAR is read or written, EDX is left unchanged. This facilitates multiple accesses when testing the entire cache/tag array. If the L2 cache data is read (as opposed to reading the tag information), the result (dword) is placed in EAX in the format 266 Test and Debug Chapter 13