AMD AMD-K6-2/400 User Guide - Page 319
Clock Switching Characteristics for 66MHz Bus Operation,
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23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 16.3 Clock Switching Characteristics for 66-MHz Bus Operation Table 63. CLK Switching Characteristics for 66-MHz Bus Operation Symbol Parameter Description Frequency t1 CLK Period t2 CLK High Time t3 CLK Low Time t4 CLK Fall Time t5 CLK Rise Time CLK Period Stability1 Preliminary Data Min 33.3 MHz 15.0 ns 4.0 ns 4.0 ns 0.15 ns 0.15 ns Max 66.6 MHz 30.0 ns 1.5 ns 1.5 ns 250 ps Figure Comments In Normal Mode 104 In Normal Mode 104 104 104 104 Notes: 1. The jitter frequency power spectrum peaking must occur at frequencies greater than (Frequency of CLK)/3 or less than 500 kHz. t2 2.0 V 1.5 V 0.8 V t5 Figure 104. CLK Waveform t3 t4 t1 Chapter 16 Signal Switching Characteristics 297